git.sur5r.net Git - u-boot/blob - include/configs/ge_bx50v3.h

   1 /*
   2  * Copyright (C) 2015 Timesys Corporation
   3  * Copyright (C) 2015 General Electric Company
   4  * Copyright (C) 2014 Advantech
   5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   6  *
   7  * Configuration settings for the GE MX6Q Bx50v3 boards.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __GE_BX50V3_CONFIG_H
  13 #define __GE_BX50V3_CONFIG_H
  14
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/mach-imx/gpio.h>
  17
  18 #define BX50V3_BOOTARGS_EXTRA
  19 #if defined(CONFIG_TARGET_GE_B450V3)
  20 #define CONFIG_BOARD_NAME       "General Electric B450v3"
  21 #elif defined(CONFIG_TARGET_GE_B650V3)
  22 #define CONFIG_BOARD_NAME       "General Electric B650v3"
  23 #elif defined(CONFIG_TARGET_GE_B850V3)
  24 #define CONFIG_BOARD_NAME       "General Electric B850v3"
  25 #undef BX50V3_BOOTARGS_EXTRA
  26 #define BX50V3_BOOTARGS_EXTRA   "video=DP-1:1024x768@60 " \
  27                                 "video=HDMI-A-1:1024x768@60 "
  28 #else
  29 #define CONFIG_BOARD_NAME       "General Electric BA16 Generic"
  30 #endif
  31
  32 #define CONFIG_MXC_UART_BASE    UART3_BASE
  33 #define CONSOLE_DEV     "ttymxc2"
  34
  35 #define CONFIG_SUPPORT_EMMC_BOOT
  36
  37
  38 #include "mx6_common.h"
  39 #include <linux/sizes.h>
  40
  41 #define CONFIG_CMDLINE_TAG
  42 #define CONFIG_SETUP_MEMORY_TAGS
  43 #define CONFIG_INITRD_TAG
  44 #define CONFIG_REVISION_TAG
  45 #define CONFIG_SYS_MALLOC_LEN           (10 * SZ_1M)
  46
  47 #define CONFIG_HW_WATCHDOG
  48 #define CONFIG_IMX_WATCHDOG
  49 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
  50
  51 #define CONFIG_LAST_STAGE_INIT
  52
  53 #define CONFIG_MXC_GPIO
  54 #define CONFIG_MXC_UART
  55
  56 #define CONFIG_MXC_OCOTP
  57
  58 /* SATA Configs */
  59 #ifdef CONFIG_CMD_SATA
  60 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  61 #define CONFIG_DWC_AHSATA_PORT_ID       0
  62 #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
  63 #define CONFIG_LBA48
  64 #endif
  65
  66 /* MMC Configs */
  67 #define CONFIG_FSL_ESDHC
  68 #define CONFIG_FSL_USDHC
  69 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
  70 #define CONFIG_BOUNCE_BUFFER
  71
  72 /* USB Configs */
  73 #ifdef CONFIG_USB
  74 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  75 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  76 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
  77 #define CONFIG_MXC_USB_FLAGS    0
  78
  79 #define CONFIG_USBD_HS
  80 #define CONFIG_USB_GADGET_MASS_STORAGE
  81 #endif
  82
  83 /* Networking Configs */
  84 #ifdef CONFIG_NET
  85 #define CONFIG_FEC_MXC
  86 #define CONFIG_MII
  87 #define IMX_FEC_BASE                    ENET_BASE_ADDR
  88 #define CONFIG_FEC_XCV_TYPE             RGMII
  89 #define CONFIG_ETHPRIME         "FEC"
  90 #define CONFIG_FEC_MXC_PHYADDR          4
  91 #define CONFIG_PHY_ATHEROS
  92 #endif
  93
  94 /* Serial Flash */
  95 #ifdef CONFIG_CMD_SF
  96 #define CONFIG_MXC_SPI
  97 #define CONFIG_SF_DEFAULT_BUS           0
  98 #define CONFIG_SF_DEFAULT_CS            0
  99 #define CONFIG_SF_DEFAULT_SPEED 20000000
 100 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 101 #endif
 102
 103 /* allow to overwrite serial and ethaddr */
 104 #define CONFIG_ENV_OVERWRITE
 105 #define CONFIG_CONS_INDEX       1
 106
 107 #define CONFIG_LOADADDR 0x12000000
 108 #define CONFIG_SYS_TEXT_BASE    0x17800000
 109
 110 #define CONFIG_EXTRA_ENV_SETTINGS \
 111         "script=boot.scr\0" \
 112         "image=/boot/fitImage\0" \
 113         "console=" CONSOLE_DEV "\0" \
 114         "fdt_high=0xffffffff\0"   \
 115         "sddev=0\0" \
 116         "emmcdev=1\0" \
 117         "partnum=1\0" \
 118         "setargs=setenv bootargs console=${console},${baudrate} " \
 119                 "root=/dev/${rootdev} rw rootwait cma=128M " \
 120                 BX50V3_BOOTARGS_EXTRA "\0" \
 121         "loadimage=" \
 122                 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 123         "tryboot=" \
 124                 "if run loadimage; then " \
 125                         "run doboot; " \
 126                 "fi;\0" \
 127         "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
 128                 "run setargs; " \
 129                 "bootm ${loadaddr}#conf@${confidx};\0 " \
 130
 131 #define CONFIG_MMCBOOTCOMMAND \
 132         "setenv dev mmc; " \
 133         "setenv rootdev mmcblk0p${partnum}; " \
 134         \
 135         "setenv devnum ${sddev}; " \
 136         "if mmc dev ${devnum}; then " \
 137                 "run tryboot; " \
 138                 "setenv rootdev mmcblk1p${partnum}; " \
 139         "fi; " \
 140         \
 141         "setenv devnum ${emmcdev}; " \
 142         "if mmc dev ${devnum}; then " \
 143                 "run tryboot; " \
 144         "fi; " \
 145
 146 #define CONFIG_USBBOOTCOMMAND \
 147         "echo Unsupported; " \
 148
 149 #ifdef CONFIG_CMD_USB
 150 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
 151 #else
 152 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
 153 #endif
 154
 155 #define CONFIG_ARP_TIMEOUT     200UL
 156
 157 /* Miscellaneous configurable options */
 158 #define CONFIG_SYS_LONGHELP
 159 #define CONFIG_AUTO_COMPLETE
 160
 161 #define CONFIG_SYS_MEMTEST_START       0x10000000
 162 #define CONFIG_SYS_MEMTEST_END         0x10010000
 163 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 164
 165 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 166
 167 #define CONFIG_CMDLINE_EDITING
 168
 169 /* Physical Memory Map */
 170 #define CONFIG_NR_DRAM_BANKS           1
 171 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 172
 173 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 174 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
 175 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 176
 177 #define CONFIG_SYS_INIT_SP_OFFSET \
 178         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 179 #define CONFIG_SYS_INIT_SP_ADDR \
 180         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 181
 182 /* environment organization */
 183 #define CONFIG_ENV_SIZE         (8 * 1024)
 184 #define CONFIG_ENV_OFFSET               (768 * 1024)
 185 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 186 #define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
 187 #define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
 188 #define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
 189 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 190
 191 #ifndef CONFIG_SYS_DCACHE_OFF
 192 #endif
 193
 194 #define CONFIG_SYS_FSL_USDHC_NUM        3
 195
 196 /* Framebuffer */
 197 #ifdef CONFIG_VIDEO
 198 #define CONFIG_VIDEO_IPUV3
 199 #define CONFIG_VIDEO_BMP_RLE8
 200 #define CONFIG_SPLASH_SCREEN
 201 #define CONFIG_SPLASH_SCREEN_ALIGN
 202 #define CONFIG_BMP_16BPP
 203 #define CONFIG_VIDEO_LOGO
 204 #define CONFIG_VIDEO_BMP_LOGO
 205 #define CONFIG_IMX_HDMI
 206 #define CONFIG_IMX_VIDEO_SKIP
 207 #endif
 208
 209 #define CONFIG_PWM_IMX
 210 #define CONFIG_IMX6_PWM_PER_CLK 66000000
 211
 212 #define CONFIG_PCI
 213 #define CONFIG_PCI_PNP
 214 #define CONFIG_PCI_SCAN_SHOW
 215 #define CONFIG_PCIE_IMX
 216 #define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
 217 #define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
 218
 219 /* I2C Configs */
 220 #define CONFIG_SYS_I2C
 221 #define CONFIG_SYS_I2C_MXC
 222 #define CONFIG_SYS_I2C_SPEED              100000
 223 #define CONFIG_SYS_I2C_MXC_I2C1
 224 #define CONFIG_SYS_I2C_MXC_I2C2
 225 #define CONFIG_SYS_I2C_MXC_I2C3
 226
 227 #define CONFIG_SYS_NUM_I2C_BUSES        11
 228 #define CONFIG_SYS_I2C_MAX_HOPS         1
 229 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 230                                         {1, {I2C_NULL_HOP} }, \
 231                                         {2, {I2C_NULL_HOP} }, \
 232                                         {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
 233                                         {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 234                                         {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 235                                         {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
 236                                         {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
 237                                         {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
 238                                         {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
 239                                         {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
 240                                 }
 241
 242 #define CONFIG_BCH
 243
 244 #endif  /* __GE_BX50V3_CONFIG_H */