1 /* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
12 * SPDX-License-Identifier: GPL-2.0+
19 * High Level Configuration Options
23 /* Altera NIOS Development board, Stratix II board */
24 #define CONFIG_GR_EP2S60 1
26 /* CPU / AMBA BUS configuration */
27 #define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
29 /* Define this is the GR-2S60-MEZZ mezzanine is available and you
30 * want to use the USB and GRETH functionality of the board
40 * Serial console configuration
42 #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
43 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
50 #define CONFIG_CMD_REGINFO
51 #define CONFIG_CMD_DIAG
52 #define CONFIG_CMD_IRQ
56 #define CONFIG_USB_UHCI
57 /* Enable needed helper functions */
64 #define CONFIG_PREBOOT "echo;" \
65 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
68 #undef CONFIG_BOOTARGS
70 #define CONFIG_EXTRA_ENV_SETTINGS \
72 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
73 "nfsroot=${serverip}:${rootpath}\0" \
74 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
75 "addip=setenv bootargs ${bootargs} " \
76 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
77 ":${hostname}:${netdev}:off panic=1\0" \
78 "flash_nfs=run nfsargs addip;" \
79 "bootm ${kernel_addr}\0" \
80 "flash_self=run ramargs addip;" \
81 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
82 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
83 "scratch=40800000\0" \
84 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
85 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
88 #define CONFIG_NETMASK 255.255.255.0
89 #define CONFIG_GATEWAYIP 192.168.0.1
90 #define CONFIG_SERVERIP 192.168.0.20
91 #define CONFIG_IPADDR 192.168.0.207
92 #define CONFIG_ROOTPATH "/export/rootfs"
93 #define CONFIG_HOSTNAME ml401
94 #define CONFIG_BOOTFILE "/uImage"
96 #define CONFIG_BOOTCOMMAND "run flash_self"
101 * |--------------------------------|
102 * | 0x00000000 Text & Data & BSS | *
104 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
105 * | UNUSED / Growth | * 256kb
106 * |--------------------------------|
107 * | 0x00050000 Base custom area | *
109 * | | * Rest of Flash
110 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
111 * | END-0x00008000 Environment | * 32kb
112 * |--------------------------------|
117 * |--------------------------------|
118 * | UNUSED / scratch area |
123 * |--------------------------------|
124 * | Monitor .Text / .DATA / .BSS | * 512kb
126 * |--------------------------------|
127 * | Monitor Malloc | * 128kb (contains relocated environment)
128 * |--------------------------------|
129 * | Monitor/kernel STACK | * 64kb
130 * |--------------------------------|
131 * | Page Table for MMU systems | * 2k
132 * |--------------------------------|
133 * | PROM Code accessed from Linux | * 6kb-128b
134 * |--------------------------------|
135 * | Global data (avail from kernel)| * 128b
136 * |--------------------------------|
141 * Flash configuration (8,16 or 32 MB)
142 * TEXT base always at 0xFFF00000
143 * ENV_ADDR always at 0xFFF40000
144 * FLASH_BASE at 0xFC000000 for 64 MB
145 * 0xFE000000 for 32 MB
146 * 0xFF000000 for 16 MB
147 * 0xFF800000 for 8 MB
149 #define CONFIG_SYS_FLASH_BASE 0x00000000
150 #define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
152 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
153 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
156 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
158 #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
159 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
160 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
163 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
164 #define CONFIG_FLASH_CFI_DRIVER
165 #define CONFIG_SYS_FLASH_CFI
166 /* Bypass cache when reading regs from flash memory */
167 #define CONFIG_SYS_FLASH_CFI_BYPASS_READ
168 /* Buffered writes (32byte/go) instead of single accesses */
169 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
172 * Environment settings
174 /*#define CONFIG_ENV_IS_NOWHERE 1*/
175 #define CONFIG_ENV_IS_IN_FLASH 1
176 /* CONFIG_ENV_ADDR need to be at sector boundary */
177 #define CONFIG_ENV_SIZE 0x8000
178 #define CONFIG_ENV_SECT_SIZE 0x20000
179 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
180 #define CONFIG_ENV_OVERWRITE 1
185 #define CONFIG_SYS_SDRAM_BASE 0x40000000
186 #define CONFIG_SYS_SDRAM_SIZE 0x02000000
187 #define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
189 /* no SRAM available */
190 #undef CONFIG_SYS_SRAM_BASE
191 #undef CONFIG_SYS_SRAM_SIZE
193 #define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
194 #define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
195 #define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
199 #define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
202 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
203 #define CONFIG_SYS_STACK_SIZE (0x10000-32)
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
206 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
207 # define CONFIG_SYS_RAMBOOT 1
210 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
211 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
212 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214 #define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
215 #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
217 /* relocated monitor area */
218 #define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
219 #define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
221 /* make un relocated address from relocated address */
222 #define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
225 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
226 * with a PHY is attached the GRETH can be used on this board.
227 * Define USE_GRETH in order to use the mezzanine provided PHY with the
228 * onchip GRETH network MAC, note that this is not supported by the
233 /* USE SMC91C111 MAC */
234 #define CONFIG_SMC91111 1
235 #define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
236 #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
237 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
238 /*#define CONFIG_SHOW_ACTIVITY*/
239 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
243 /* USE GRETH Ethernet Driver */
244 #define CONFIG_GRETH 1
247 #define CONFIG_PHY_ADDR 0x00
250 * Miscellaneous configurable options
252 #define CONFIG_SYS_LONGHELP /* undef to save memory */
253 #if defined(CONFIG_CMD_KGDB)
254 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
256 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
258 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
259 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
260 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
262 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
263 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
265 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
267 /*-----------------------------------------------------------------------
269 *-----------------------------------------------------------------------
271 #define CONFIG_USB_CLOCK 0x0001BBBB
272 #define CONFIG_USB_CONFIG 0x00005000
274 /***** Gaisler GRLIB IP-Cores Config ********/
276 #define CONFIG_SYS_GRLIB_SDRAM 0
278 /* No SDRAM Configuration */
279 #undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
281 /* See, GRLIB Docs (grip.pdf) on how to set up
282 * These the memory controller registers.
284 #define CONFIG_SYS_GRLIB_ESA_MCTRL1
285 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
286 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
287 #define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
289 /* GRLIB FT-MCTRL configuration */
290 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
291 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
292 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
293 #define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
296 #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
297 #define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
299 /* no DDR2 Controller */
300 #undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
302 /* default kernel command line */
303 #define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
305 #endif /* __CONFIG_H */