3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is a MPC860T CPU */
37 #define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE
42 #define CONFIG_BAUDRATE 9600
44 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
51 #define CONFIG_BOARD_TYPES 1 /* support board types */
53 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
55 #undef CONFIG_BOOTARGS
56 #define CONFIG_BOOTCOMMAND \
58 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
62 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
69 * Command line configuration.
71 #include <config_cmd_default.h>
74 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
77 * Miscellaneous configurable options
79 #define CFG_LONGHELP /* undef to save memory */
80 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
81 #if defined(CONFIG_CMD_KGDB)
82 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
84 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
86 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
87 #define CFG_MAXARGS 16 /* max number of command args */
88 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
90 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
91 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
93 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
95 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
97 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
99 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
101 #define CFG_ALLOC_DPRAM 1 /* use allocation routines */
103 * Low Level Configuration Settings
104 * (address mappings, register initial values, etc.)
105 * You should know what you are doing if you make changes here.
107 /*-----------------------------------------------------------------------
108 * Internal Memory Mapped Register
110 #define CFG_IMMR 0xFF000000 /* Non-Standard value! */
112 /*-----------------------------------------------------------------------
113 * Definitions for initial stack pointer and data area (in DPRAM)
115 #define CFG_INIT_RAM_ADDR CFG_IMMR
116 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
117 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
118 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
119 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
121 /*-----------------------------------------------------------------------
122 * Start addresses for the final memory configuration
123 * (Set up by the startup code)
124 * Please note that CFG_SDRAM_BASE _must_ start at 0
126 #define CFG_SDRAM_BASE 0x00000000
127 #define CFG_FLASH_BASE 0xFE000000
129 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
131 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
133 #define CFG_MONITOR_BASE CFG_FLASH_BASE
134 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
137 * For booting Linux, the board info and command line data
138 * have to be in the first 8 MB of memory, since this is
139 * the maximum mapped by the Linux kernel during initialization.
141 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
142 /*-----------------------------------------------------------------------
145 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
146 #define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
148 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
149 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
151 #define CFG_ENV_IS_IN_FLASH 1
152 #define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
153 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
154 /*-----------------------------------------------------------------------
155 * Cache Configuration
157 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
158 #if defined(CONFIG_CMD_KGDB)
159 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
162 /*-----------------------------------------------------------------------
163 * SYPCR - System Protection Control 11-9
164 * SYPCR can only be written once after reset!
165 *-----------------------------------------------------------------------
166 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
169 #if defined(CONFIG_WATCHDOG)
170 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
171 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
173 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
176 /*-----------------------------------------------------------------------
177 * SIUMCR - SIU Module Configuration 11-6
178 *-----------------------------------------------------------------------
179 * +0x0000 => 0x000000C0
183 /*-----------------------------------------------------------------------
184 * TBSCR - Time Base Status and Control 11-26
185 *-----------------------------------------------------------------------
186 * Clear Reference Interrupt Status, Timebase freezing enabled
189 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
191 /*-----------------------------------------------------------------------
192 * PISCR - Periodic Interrupt Status and Control 11-31
193 *-----------------------------------------------------------------------
194 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
197 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
199 /*-----------------------------------------------------------------------
200 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
201 *-----------------------------------------------------------------------
202 * Reset PLL lock status sticky bit, timer expired status bit and timer
203 * interrupt status bit, set PLL multiplication factor !
205 /* +0x0286 => 0x00B0D0C0 */
207 ( (11 << PLPRCR_MF_SHIFT) | \
208 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
209 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
210 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
213 /*-----------------------------------------------------------------------
214 * SCCR - System Clock and reset Control Register 15-27
215 *-----------------------------------------------------------------------
216 * Set clock output, timebase and RTC source and divider,
217 * power management and some other internal clocks
219 #define SCCR_MASK SCCR_EBDF11
220 /* +0x0282 => 0x03800000 */
221 #define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
222 SCCR_RTDIV | SCCR_RTSEL | \
223 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
224 SCCR_EBDF00 | SCCR_DFSYNC00 | \
225 SCCR_DFBRG00 | SCCR_DFNL000 | \
228 /*-----------------------------------------------------------------------
229 * RTCSC - Real-Time Clock Status and Control Register 11-27
230 *-----------------------------------------------------------------------
232 /* +0x0220 => 0x00C3 */
233 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
236 /*-----------------------------------------------------------------------
237 * RCCR - RISC Controller Configuration Register 19-4
238 *-----------------------------------------------------------------------
240 /* +0x09C4 => TIMEP=1 */
241 #define CFG_RCCR 0x0100
243 /*-----------------------------------------------------------------------
244 * RMDS - RISC Microcode Development Support Control Register
245 *-----------------------------------------------------------------------
249 /*-----------------------------------------------------------------------
251 *-----------------------------------------------------------------------
257 * Init Memory Controller:
259 * BR0 and OR0 (FLASH)
262 #define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
264 /* used to re-map FLASH
265 * restrict access enough to keep SRAM working (if any)
266 * but not too much to meddle with FLASH accesses
268 /* allow for max 4 MB of Flash */
269 #define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
270 #define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
272 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
273 #define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
274 OR_SCY_5_CLK | OR_TRLX)
276 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
277 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
278 /* 8 bit, bank valid */
279 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
284 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
286 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
287 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
288 #define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
290 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
292 #define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
293 #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
296 * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
298 #define HPRO2_BASE 0xE0000000
299 #define HPRO2_OR_AM 0xFFFF8000
300 #define HPRO2_TIMING 0x00000934
302 #define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
303 #define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
314 * MAMR settings for SDRAM
317 /* periodic timer for refresh */
318 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
321 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
322 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
323 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
325 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
326 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
327 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
330 * Internal Definitions
334 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
335 #define BOOTFLAG_WARM 0x02 /* Software reboot */
337 #endif /* __CONFIG_H */