2 * Copyright 2010-2011 Calxeda, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_SYS_NO_FLASH
14 #define CONFIG_SYS_HZ CFG_HZ
16 #define CONFIG_OF_LIBFDT
18 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)
21 * Size of malloc() pool
23 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
25 #define CONFIG_PL011_SERIAL
26 #define CONFIG_PL011_CLOCK 150000000
27 #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
28 #define CONFIG_CONS_INDEX 0
30 #define CONFIG_BAUDRATE 38400
32 #define CONFIG_BOOTCOUNT_LIMIT
33 #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
34 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
35 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c
37 #define CONFIG_MISC_INIT_R
38 #define CONFIG_SCSI_AHCI
39 #define CONFIG_SCSI_AHCI_PLAT
40 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
41 #define CONFIG_SYS_SCSI_MAX_LUN 1
42 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
43 CONFIG_SYS_SCSI_MAX_LUN)
45 #define CONFIG_DOS_PARTITION
47 #define CONFIG_CALXEDA_XGMAC
50 #define CONFIG_BOOTP_PXE
51 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
52 #define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.highbank"
55 * Command line configuration.
57 #include <config_cmd_default.h>
59 #define CONFIG_CMD_BDI
60 #define CONFIG_CMD_DHCP
61 #define CONFIG_CMD_ELF
62 #define CONFIG_CMD_MEMORY
63 #define CONFIG_CMD_LOADS
64 #define CONFIG_CMD_SCSI
65 #define CONFIG_CMD_EXT2
66 #define CONFIG_CMD_PXE
69 #define CONFIG_BOOTDELAY 2
71 * Miscellaneous configurable options
73 #define CONFIG_CMDLINE_EDITING
74 #define CONFIG_AUTO_COMPLETE
75 #define CONFIG_SYS_LONGHELP /* undef to save memory */
76 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
77 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
78 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
79 #define CONFIG_SYS_PROMPT "Highbank #"
80 /* Print Buffer Size */
81 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
82 sizeof(CONFIG_SYS_PROMPT)+16)
84 #define CONFIG_SYS_LOAD_ADDR 0x800000
86 /*-----------------------------------------------------------------------
89 #define CONFIG_NR_DRAM_BANKS 1
90 #define PHYS_SDRAM_1_SIZE (4089 << 20)
91 #define CONFIG_SYS_MEMTEST_START 0x100000
92 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)
94 /* Environment data setup
96 #define CONFIG_ENV_IS_IN_NVRAM
97 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
98 #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
99 #define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */
100 #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
102 #define CONFIG_SYS_SDRAM_BASE 0x00000000
103 #define CONFIG_SYS_TEXT_BASE 0x00008000
104 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000
105 #define CONFIG_SKIP_LOWLEVEL_INIT