2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
16 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
17 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
18 #define CONFIG_HMI1001 1 /* HMI1001 board */
20 #ifndef CONFIG_SYS_TEXT_BASE
21 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
24 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
26 #define CONFIG_BOARD_EARLY_INIT_R
28 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
31 * Serial console configuration
33 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
34 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
35 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
38 #define CONFIG_DOS_PARTITION
44 #define CONFIG_BOOTP_BOOTFILESIZE
45 #define CONFIG_BOOTP_BOOTPATH
46 #define CONFIG_BOOTP_GATEWAY
47 #define CONFIG_BOOTP_HOSTNAME
51 * Command line configuration.
53 #include <config_cmd_default.h>
55 #define CONFIG_CMD_DATE
56 #define CONFIG_CMD_DISPLAY
57 #define CONFIG_CMD_DHCP
58 #define CONFIG_CMD_EEPROM
59 #define CONFIG_CMD_I2C
60 #define CONFIG_CMD_IDE
61 #define CONFIG_CMD_NFS
62 #define CONFIG_CMD_PCI
63 #define CONFIG_CMD_SNTP
66 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
68 #if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
69 # define CONFIG_SYS_LOWBOOT 1
75 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
77 #define CONFIG_PREBOOT "echo;" \
78 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
81 #undef CONFIG_BOOTARGS
83 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "nfsargs=setenv bootargs root=/dev/nfs rw " \
86 "nfsroot=${serverip}:${rootpath}\0" \
87 "ramargs=setenv bootargs root=/dev/ram rw\0" \
88 "addip=setenv bootargs ${bootargs} " \
89 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
90 ":${hostname}:${netdev}:off panic=1\0" \
91 "flash_nfs=run nfsargs addip;" \
92 "bootm ${kernel_addr}\0" \
93 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
94 "rootpath=/opt/eldk/ppc_82xx\0" \
97 #define CONFIG_BOOTCOMMAND "run net_nfs"
99 #define CONFIG_MISC_INIT_R 1
102 * IPB Bus clocking configuration.
104 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
109 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
110 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
112 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
113 #define CONFIG_SYS_I2C_SLAVE 0x7F
116 * EEPROM configuration
118 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
120 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
121 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
126 #define CONFIG_RTC_PCF8563
127 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
130 * Flash configuration
132 #define CONFIG_SYS_FLASH_BASE 0xFF800000
134 #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
135 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
137 #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
138 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
140 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
141 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
143 #define CONFIG_FLASH_CFI_DRIVER
144 #define CONFIG_SYS_FLASH_CFI
145 #define CONFIG_SYS_FLASH_EMPTY_INFO
146 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
149 * Environment settings
151 #define CONFIG_ENV_IS_IN_FLASH 1
152 #define CONFIG_ENV_SIZE 0x4000
153 #define CONFIG_ENV_SECT_SIZE 0x20000
154 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
155 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
160 #define CONFIG_SYS_MBAR 0xF0000000
161 #define CONFIG_SYS_SDRAM_BASE 0x00000000
162 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
163 #define CONFIG_SYS_DISPLAY_BASE 0x80600000
164 #define CONFIG_SYS_STATUS1_BASE 0x80600200
165 #define CONFIG_SYS_STATUS2_BASE 0x80600300
167 /* Settings for XLB = 132 MHz */
169 #define SDRAM_MODE 0x018D0000
170 #define SDRAM_EMODE 0x40090000
171 #define SDRAM_CONTROL 0x714f0f00
172 #define SDRAM_CONFIG1 0x73722930
173 #define SDRAM_CONFIG2 0x47770000
174 #define SDRAM_TAPDELAY 0x10000000
176 /* Use ON-Chip SRAM until RAM will be available */
177 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
179 /* preserve space for the post_word at end of on-chip SRAM */
180 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
183 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
185 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
189 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
192 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
193 # define CONFIG_SYS_RAMBOOT 1
196 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
197 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
198 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
201 * Ethernet configuration
203 #define CONFIG_MPC5xxx_FEC 1
204 #define CONFIG_MPC5xxx_FEC_MII100
205 #define CONFIG_PHY_ADDR 0x00
206 #define CONFIG_MII 1 /* MII PHY management */
211 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004
214 * Miscellaneous configurable options
216 #define CONFIG_SYS_LONGHELP /* undef to save memory */
217 #if defined(CONFIG_CMD_KGDB)
218 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
220 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
222 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
223 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
224 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
226 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
227 #if defined(CONFIG_CMD_KGDB)
228 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
231 /* Enable an alternate, more extensive memory test */
232 #define CONFIG_SYS_ALT_MEMTEST
234 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
235 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
237 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
239 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
242 * Enable loopw command.
247 * Various low-level settings
249 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
250 #define CONFIG_SYS_HID0_FINAL HID0_ICE
252 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
253 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
254 #define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
255 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
256 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
258 /* 8Mbit SRAM @0x80100000 */
259 #define CONFIG_SYS_CS1_START 0x80100000
260 #define CONFIG_SYS_CS1_SIZE 0x00100000
261 #define CONFIG_SYS_CS1_CFG 0x19B00
263 /* FRAM 32Kbyte @0x80700000 */
264 #define CONFIG_SYS_CS2_START 0x80700000
265 #define CONFIG_SYS_CS2_SIZE 0x00008000
266 #define CONFIG_SYS_CS2_CFG 0x19800
268 /* Display H1, Status Inputs, EPLD @0x80600000 */
269 #define CONFIG_SYS_CS3_START 0x80600000
270 #define CONFIG_SYS_CS3_SIZE 0x00100000
271 #define CONFIG_SYS_CS3_CFG 0x00019800
273 #define CONFIG_SYS_CS_BURST 0x00000000
274 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
276 /*-----------------------------------------------------------------------
277 * IDE/ATA stuff Supports IDE harddisk
278 *-----------------------------------------------------------------------
281 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
283 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
284 #undef CONFIG_IDE_LED /* LED for ide not supported */
286 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
287 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
289 #define CONFIG_IDE_PREINIT 1
291 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
293 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
295 /* Offset for data I/O */
296 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
298 /* Offset for normal register accesses */
299 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
301 /* Offset for alternate registers */
302 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
304 /* Interval between registers */
305 #define CONFIG_SYS_ATA_STRIDE 4
307 #define CONFIG_ATAPI 1
309 #define CONFIG_VIDEO_SMI_LYNXEM
310 #define CONFIG_CFB_CONSOLE
311 #define CONFIG_VGA_AS_SINGLE_DEVICE
312 #define CONFIG_VIDEO_LOGO
316 * 0x40000000 - 0x4fffffff - PCI Memory
317 * 0x50000000 - 0x50ffffff - PCI IO Space
320 #define CONFIG_PCI_PNP 1
321 #define CONFIG_PCI_SCAN_SHOW 1
322 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
324 #define CONFIG_PCI_MEM_BUS 0x40000000
325 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
326 #define CONFIG_PCI_MEM_SIZE 0x10000000
328 #define CONFIG_PCI_IO_BUS 0x50000000
329 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
330 #define CONFIG_PCI_IO_SIZE 0x01000000
332 #define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
334 /*---------------------------------------------------------------------*/
335 /* Display addresses */
336 /*---------------------------------------------------------------------*/
338 #define CONFIG_PDSP188x
339 #define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
340 #define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
342 #endif /* __CONFIG_H */