2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_HMI1001 1 /* HMI1001 board */
36 #ifndef CONFIG_SYS_TEXT_BASE
37 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
40 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
42 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
43 #define BOOTFLAG_WARM 0x02 /* Software reboot */
45 #define CONFIG_BOARD_EARLY_INIT_R
47 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
50 * Serial console configuration
52 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
54 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57 #define CONFIG_DOS_PARTITION
63 #define CONFIG_BOOTP_BOOTFILESIZE
64 #define CONFIG_BOOTP_BOOTPATH
65 #define CONFIG_BOOTP_GATEWAY
66 #define CONFIG_BOOTP_HOSTNAME
70 * Command line configuration.
72 #include <config_cmd_default.h>
74 #define CONFIG_CMD_DATE
75 #define CONFIG_CMD_DISPLAY
76 #define CONFIG_CMD_DHCP
77 #define CONFIG_CMD_EEPROM
78 #define CONFIG_CMD_I2C
79 #define CONFIG_CMD_IDE
80 #define CONFIG_CMD_NFS
81 #define CONFIG_CMD_PCI
82 #define CONFIG_CMD_SNTP
85 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
87 #if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
88 # define CONFIG_SYS_LOWBOOT 1
94 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
96 #define CONFIG_PREBOOT "echo;" \
97 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
100 #undef CONFIG_BOOTARGS
102 #define CONFIG_EXTRA_ENV_SETTINGS \
104 "nfsargs=setenv bootargs root=/dev/nfs rw " \
105 "nfsroot=${serverip}:${rootpath}\0" \
106 "ramargs=setenv bootargs root=/dev/ram rw\0" \
107 "addip=setenv bootargs ${bootargs} " \
108 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
109 ":${hostname}:${netdev}:off panic=1\0" \
110 "flash_nfs=run nfsargs addip;" \
111 "bootm ${kernel_addr}\0" \
112 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
113 "rootpath=/opt/eldk/ppc_82xx\0" \
116 #define CONFIG_BOOTCOMMAND "run net_nfs"
118 #define CONFIG_MISC_INIT_R 1
121 * IPB Bus clocking configuration.
123 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
128 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
129 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
131 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
132 #define CONFIG_SYS_I2C_SLAVE 0x7F
135 * EEPROM configuration
137 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
139 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
140 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
145 #define CONFIG_RTC_PCF8563
146 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
149 * Flash configuration
151 #define CONFIG_SYS_FLASH_BASE 0xFF800000
153 #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
154 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
156 #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
159 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
162 #define CONFIG_FLASH_CFI_DRIVER
163 #define CONFIG_SYS_FLASH_CFI
164 #define CONFIG_SYS_FLASH_EMPTY_INFO
165 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
168 * Environment settings
170 #define CONFIG_ENV_IS_IN_FLASH 1
171 #define CONFIG_ENV_SIZE 0x4000
172 #define CONFIG_ENV_SECT_SIZE 0x20000
173 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
174 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
179 #define CONFIG_SYS_MBAR 0xF0000000
180 #define CONFIG_SYS_SDRAM_BASE 0x00000000
181 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
182 #define CONFIG_SYS_DISPLAY_BASE 0x80600000
183 #define CONFIG_SYS_STATUS1_BASE 0x80600200
184 #define CONFIG_SYS_STATUS2_BASE 0x80600300
186 /* Settings for XLB = 132 MHz */
188 #define SDRAM_MODE 0x018D0000
189 #define SDRAM_EMODE 0x40090000
190 #define SDRAM_CONTROL 0x714f0f00
191 #define SDRAM_CONFIG1 0x73722930
192 #define SDRAM_CONFIG2 0x47770000
193 #define SDRAM_TAPDELAY 0x10000000
195 /* Use ON-Chip SRAM until RAM will be available */
196 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
198 /* preserve space for the post_word at end of on-chip SRAM */
199 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
202 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
204 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
207 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
212 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
213 # define CONFIG_SYS_RAMBOOT 1
216 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
217 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
218 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
221 * Ethernet configuration
223 #define CONFIG_MPC5xxx_FEC 1
224 #define CONFIG_MPC5xxx_FEC_MII100
225 #define CONFIG_PHY_ADDR 0x00
226 #define CONFIG_MII 1 /* MII PHY management */
231 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004
234 * Miscellaneous configurable options
236 #define CONFIG_SYS_LONGHELP /* undef to save memory */
237 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
238 #if defined(CONFIG_CMD_KGDB)
239 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
241 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
244 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
247 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
248 #if defined(CONFIG_CMD_KGDB)
249 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
252 /* Enable an alternate, more extensive memory test */
253 #define CONFIG_SYS_ALT_MEMTEST
255 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
256 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
258 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
260 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
263 * Enable loopw command.
268 * Various low-level settings
270 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
271 #define CONFIG_SYS_HID0_FINAL HID0_ICE
273 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
274 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
275 #define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
276 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
277 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
279 /* 8Mbit SRAM @0x80100000 */
280 #define CONFIG_SYS_CS1_START 0x80100000
281 #define CONFIG_SYS_CS1_SIZE 0x00100000
282 #define CONFIG_SYS_CS1_CFG 0x19B00
284 /* FRAM 32Kbyte @0x80700000 */
285 #define CONFIG_SYS_CS2_START 0x80700000
286 #define CONFIG_SYS_CS2_SIZE 0x00008000
287 #define CONFIG_SYS_CS2_CFG 0x19800
289 /* Display H1, Status Inputs, EPLD @0x80600000 */
290 #define CONFIG_SYS_CS3_START 0x80600000
291 #define CONFIG_SYS_CS3_SIZE 0x00100000
292 #define CONFIG_SYS_CS3_CFG 0x00019800
294 #define CONFIG_SYS_CS_BURST 0x00000000
295 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
297 /*-----------------------------------------------------------------------
298 * IDE/ATA stuff Supports IDE harddisk
299 *-----------------------------------------------------------------------
302 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
304 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
305 #undef CONFIG_IDE_LED /* LED for ide not supported */
307 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
308 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
310 #define CONFIG_IDE_PREINIT 1
312 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
314 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
316 /* Offset for data I/O */
317 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
319 /* Offset for normal register accesses */
320 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
322 /* Offset for alternate registers */
323 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
325 /* Interval between registers */
326 #define CONFIG_SYS_ATA_STRIDE 4
328 #define CONFIG_ATAPI 1
330 #define CONFIG_VIDEO_SMI_LYNXEM
331 #define CONFIG_CFB_CONSOLE
332 #define CONFIG_VGA_AS_SINGLE_DEVICE
333 #define CONFIG_VIDEO_LOGO
337 * 0x40000000 - 0x4fffffff - PCI Memory
338 * 0x50000000 - 0x50ffffff - PCI IO Space
341 #define CONFIG_PCI_PNP 1
342 #define CONFIG_PCI_SCAN_SHOW 1
343 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
345 #define CONFIG_PCI_MEM_BUS 0x40000000
346 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
347 #define CONFIG_PCI_MEM_SIZE 0x10000000
349 #define CONFIG_PCI_IO_BUS 0x50000000
350 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
351 #define CONFIG_PCI_IO_SIZE 0x01000000
353 #define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
355 /*---------------------------------------------------------------------*/
356 /* Display addresses */
357 /*---------------------------------------------------------------------*/
359 #define CONFIG_PDSP188x
360 #define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
361 #define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
363 #endif /* __CONFIG_H */