git.sur5r.net Git - u-boot/blob - include/configs/hrcon.h

   1 /*
   2  * (C) Copyright 2014
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  17 #define CONFIG_MPC830x          1 /* MPC830x family */
  18 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  19 #define CONFIG_HRCON            1 /* HRCON board specific */
  20
  21 #define CONFIG_BOARD_EARLY_INIT_R
  22 #define CONFIG_LAST_STAGE_INIT
  23
  24 #define CONFIG_FSL_ESDHC
  25 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  26
  27 /*
  28  * System Clock Setup
  29  */
  30 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  31 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  32
  33 /*
  34  * Hardware Reset Configuration Word
  35  * if CLKIN is 66.66MHz, then
  36  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  37  * We choose the A type silicon as default, so the core is 400Mhz.
  38  */
  39 #define CONFIG_SYS_HRCW_LOW (\
  40         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  41         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  42         HRCWL_SVCOD_DIV_2 |\
  43         HRCWL_CSB_TO_CLKIN_4X1 |\
  44         HRCWL_CORE_TO_CSB_3X1)
  45 /*
  46  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  47  * in 8308's HRCWH according to the manual, but original Freescale's
  48  * code has them and I've expirienced some problems using the board
  49  * with BDI3000 attached when I've tried to set these bits to zero
  50  * (UART doesn't work after the 'reset run' command).
  51  */
  52 #define CONFIG_SYS_HRCW_HIGH (\
  53         HRCWH_PCI_HOST |\
  54         HRCWH_PCI1_ARBITER_ENABLE |\
  55         HRCWH_CORE_ENABLE |\
  56         HRCWH_FROM_0XFFF00100 |\
  57         HRCWH_BOOTSEQ_DISABLE |\
  58         HRCWH_SW_WATCHDOG_DISABLE |\
  59         HRCWH_ROM_LOC_LOCAL_16BIT |\
  60         HRCWH_RL_EXT_LEGACY |\
  61         HRCWH_TSEC1M_IN_RGMII |\
  62         HRCWH_TSEC2M_IN_RGMII |\
  63         HRCWH_BIG_ENDIAN)
  64
  65 /*
  66  * System IO Config
  67  */
  68 #define CONFIG_SYS_SICRH (\
  69         SICRH_ESDHC_A_SD |\
  70         SICRH_ESDHC_B_SD |\
  71         SICRH_ESDHC_C_SD |\
  72         SICRH_GPIO_A_GPIO |\
  73         SICRH_GPIO_B_GPIO |\
  74         SICRH_IEEE1588_A_GPIO |\
  75         SICRH_USB |\
  76         SICRH_GTM_GPIO |\
  77         SICRH_IEEE1588_B_GPIO |\
  78         SICRH_ETSEC2_GPIO |\
  79         SICRH_GPIOSEL_1 |\
  80         SICRH_TMROBI_V3P3 |\
  81         SICRH_TSOBI1_V2P5 |\
  82         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  83 #define CONFIG_SYS_SICRL (\
  84         SICRL_SPI_PF0 |\
  85         SICRL_UART_PF0 |\
  86         SICRL_IRQ_PF0 |\
  87         SICRL_I2C2_PF0 |\
  88         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  89
  90 /*
  91  * IMMR new address
  92  */
  93 #define CONFIG_SYS_IMMR         0xE0000000
  94
  95 /*
  96  * SERDES
  97  */
  98 #define CONFIG_FSL_SERDES
  99 #define CONFIG_FSL_SERDES1      0xe3000
 100
 101 /*
 102  * Arbiter Setup
 103  */
 104 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 105 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 106 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 107
 108 /*
 109  * DDR Setup
 110  */
 111 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 112 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 113 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 114 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 115 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 116                                 | DDRCDR_PZ_LOZ \
 117                                 | DDRCDR_NZ_LOZ \
 118                                 | DDRCDR_ODT \
 119                                 | DDRCDR_Q_DRN)
 120                                 /* 0x7b880001 */
 121 /*
 122  * Manually set up DDR parameters
 123  * consist of one chip NT5TU64M16HG from NANYA
 124  */
 125
 126 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 127
 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 129 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 130                                 | CSCONFIG_ODT_RD_NEVER \
 131                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 132                                 | CSCONFIG_BANK_BIT_3 \
 133                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 134                                 /* 0x80010102 */
 135 #define CONFIG_SYS_DDR_TIMING_3 0
 136 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 137                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 138                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 139                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 140                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 141                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 142                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 143                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 144                                 /* 0x00260802 */
 145 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 146                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 147                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 148                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 149                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 150                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 151                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 152                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 153                                 /* 0x26279222 */
 154 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 155                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 156                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 157                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 158                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 159                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 160                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 161                                 /* 0x021848c5 */
 162 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 163                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 164                                 /* 0x08240100 */
 165 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 166                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 167                                 | SDRAM_CFG_DBW_16)
 168                                 /* 0x43100000 */
 169
 170 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 171 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 172                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 173                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 174 #define CONFIG_SYS_DDR_MODE2            0x00000000
 175
 176 /*
 177  * Memory test
 178  */
 179 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 180 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 181
 182 /*
 183  * The reserved memory
 184  */
 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 186
 187 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 188 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 189
 190 /*
 191  * Initial RAM Base Address Setup
 192  */
 193 #define CONFIG_SYS_INIT_RAM_LOCK        1
 194 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 195 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 196 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 197         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 198
 199 /*
 200  * Local Bus Configuration & Clock Setup
 201  */
 202 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 203 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 204 #define CONFIG_SYS_LBC_LBCR             0x00040000
 205
 206 /*
 207  * FLASH on the Local Bus
 208  */
 209 #if 1
 210 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 211 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 212 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 213 #define CONFIG_FLASH_CFI_LEGACY
 214 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 215 #endif
 216
 217 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 218 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 219 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 220
 221 /* Window base at flash base */
 222 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 223 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 224
 225 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 226                                 | BR_PS_16      /* 16 bit port */ \
 227                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 228                                 | BR_V)         /* valid */
 229 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 230                                 | OR_UPM_XAM \
 231                                 | OR_GPCM_CSNT \
 232                                 | OR_GPCM_ACS_DIV2 \
 233                                 | OR_GPCM_XACS \
 234                                 | OR_GPCM_SCY_15 \
 235                                 | OR_GPCM_TRLX_SET \
 236                                 | OR_GPCM_EHTR_SET)
 237
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 239 #define CONFIG_SYS_MAX_FLASH_SECT       135
 240
 241 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 242 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 243
 244 /*
 245  * FPGA
 246  */
 247 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 248 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 249
 250 /* Window base at FPGA base */
 251 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 252 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 253
 254 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 255                                 | BR_PS_16      /* 16 bit port */ \
 256                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 257                                 | BR_V)         /* valid */
 258 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 259                                 | OR_UPM_XAM \
 260                                 | OR_GPCM_CSNT \
 261                                 | OR_GPCM_ACS_DIV2 \
 262                                 | OR_GPCM_XACS \
 263                                 | OR_GPCM_SCY_15 \
 264                                 | OR_GPCM_TRLX_SET \
 265                                 | OR_GPCM_EHTR_SET)
 266
 267 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 268 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 269
 270 #define CONFIG_SYS_FPGA_COUNT           1
 271
 272 #define CONFIG_SYS_MCLINK_MAX           3
 273
 274 #define CONFIG_SYS_FPGA_PTR \
 275         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 276
 277 /*
 278  * Serial Port
 279  */
 280 #define CONFIG_SYS_NS16550_SERIAL
 281 #define CONFIG_SYS_NS16550_REG_SIZE     1
 282 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 283
 284 #define CONFIG_SYS_BAUDRATE_TABLE  \
 285         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 286
 287 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 288 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 289
 290 /* Pass open firmware flat tree */
 291
 292 /* I2C */
 293 #define CONFIG_SYS_I2C
 294 #define CONFIG_SYS_I2C_FSL
 295 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 296 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 297 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 298
 299 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 300 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 301
 302 #define CONFIG_SYS_I2C_IHS
 303 #define CONFIG_SYS_I2C_IHS_CH0
 304 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 305 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 306 #define CONFIG_SYS_I2C_IHS_CH1
 307 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 308 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 309 #define CONFIG_SYS_I2C_IHS_CH2
 310 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 311 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 312 #define CONFIG_SYS_I2C_IHS_CH3
 313 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 314 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 315
 316 #ifdef CONFIG_HRCON_DH
 317 #define CONFIG_SYS_I2C_IHS_DUAL
 318 #define CONFIG_SYS_I2C_IHS_CH0_1
 319 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 320 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 321 #define CONFIG_SYS_I2C_IHS_CH1_1
 322 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 323 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 324 #define CONFIG_SYS_I2C_IHS_CH2_1
 325 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 326 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 327 #define CONFIG_SYS_I2C_IHS_CH3_1
 328 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 329 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 330 #endif
 331
 332 /*
 333  * Software (bit-bang) I2C driver configuration
 334  */
 335 #define CONFIG_SYS_I2C_SOFT
 336 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 337 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 338 #define I2C_SOFT_DECLARATIONS2
 339 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 340 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 341 #define I2C_SOFT_DECLARATIONS3
 342 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 343 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 344 #define I2C_SOFT_DECLARATIONS4
 345 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 346 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 347 #define I2C_SOFT_DECLARATIONS5
 348 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 349 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 350 #define I2C_SOFT_DECLARATIONS6
 351 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 353 #define I2C_SOFT_DECLARATIONS7
 354 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 356 #define I2C_SOFT_DECLARATIONS8
 357 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 359
 360 #ifdef CONFIG_HRCON_DH
 361 #define I2C_SOFT_DECLARATIONS9
 362 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 364 #define I2C_SOFT_DECLARATIONS10
 365 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 367 #define I2C_SOFT_DECLARATIONS11
 368 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 370 #define I2C_SOFT_DECLARATIONS12
 371 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 373 #endif
 374
 375 #ifdef CONFIG_HRCON_DH
 376 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 377 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 378 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 379                                                   {12, 0x4c} }
 380 #else
 381 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 382 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 383 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 384                                                   {8, 0x4c} }
 385 #endif
 386
 387 #ifndef __ASSEMBLY__
 388 void fpga_gpio_set(unsigned int bus, int pin);
 389 void fpga_gpio_clear(unsigned int bus, int pin);
 390 int fpga_gpio_get(unsigned int bus, int pin);
 391 void fpga_control_set(unsigned int bus, int pin);
 392 void fpga_control_clear(unsigned int bus, int pin);
 393 #endif
 394
 395 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 396 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 397 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 398
 399 #ifdef CONFIG_HRCON_DH
 400 #define I2C_ACTIVE \
 401         do { \
 402                 if (I2C_ADAP_HWNR > 7) \
 403                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 404                 else \
 405                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 406         } while (0)
 407 #else
 408 #define I2C_ACTIVE      { }
 409 #endif
 410 #define I2C_TRISTATE    { }
 411 #define I2C_READ \
 412         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 413 #define I2C_SDA(bit) \
 414         do { \
 415                 if (bit) \
 416                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 417                 else \
 418                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 419         } while (0)
 420 #define I2C_SCL(bit) \
 421         do { \
 422                 if (bit) \
 423                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 424                 else \
 425                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 426         } while (0)
 427 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 428
 429 /*
 430  * Software (bit-bang) MII driver configuration
 431  */
 432 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 433 #define CONFIG_BITBANGMII_MULTI
 434
 435 /*
 436  * OSD Setup
 437  */
 438 #define CONFIG_SYS_OSD_SCREENS          1
 439 #define CONFIG_SYS_DP501_DIFFERENTIAL
 440 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 441
 442 #ifdef CONFIG_HRCON_DH
 443 #define CONFIG_SYS_OSD_DH
 444 #endif
 445
 446 /*
 447  * General PCI
 448  * Addresses are mapped 1-1.
 449  */
 450 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 451 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 452 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 453 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 454 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 455 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 456 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 457 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 458 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 459
 460 /* enable PCIE clock */
 461 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 462
 463 #define CONFIG_PCI_INDIRECT_BRIDGE
 464 #define CONFIG_PCIE
 465
 466 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 467 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 468
 469 /*
 470  * TSEC
 471  */
 472 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 473 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 474 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 475
 476 /*
 477  * TSEC ethernet configuration
 478  */
 479 #define CONFIG_MII              1 /* MII PHY management */
 480 #define CONFIG_TSEC1
 481 #define CONFIG_TSEC1_NAME       "eTSEC0"
 482 #define TSEC1_PHY_ADDR          1
 483 #define TSEC1_PHYIDX            0
 484 #define TSEC1_FLAGS             TSEC_GIGABIT
 485
 486 /* Options are: eTSEC[0-1] */
 487 #define CONFIG_ETHPRIME         "eTSEC0"
 488
 489 /*
 490  * Environment
 491  */
 492 #if 1
 493 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 494                                  CONFIG_SYS_MONITOR_LEN)
 495 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 496 #define CONFIG_ENV_SIZE         0x2000
 497 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 498 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 499 #else
 500 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 501 #endif
 502
 503 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 504 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 505
 506 /*
 507  * Command line configuration.
 508  */
 509
 510 /*
 511  * Miscellaneous configurable options
 512  */
 513 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 514 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 515
 516 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 517
 518 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 519
 520 /*
 521  * For booting Linux, the board info and command line data
 522  * have to be in the first 256 MB of memory, since this is
 523  * the maximum mapped by the Linux kernel during initialization.
 524  */
 525 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 526
 527 /*
 528  * Core HID Setup
 529  */
 530 #define CONFIG_SYS_HID0_INIT    0x000000000
 531 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 532                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 533                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 534 #define CONFIG_SYS_HID2         HID2_HBE
 535
 536 /*
 537  * MMU Setup
 538  */
 539
 540 /* DDR: cache cacheable */
 541 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 542                                         BATL_MEMCOHERENCE)
 543 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 544                                         BATU_VS | BATU_VP)
 545 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 546 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 547
 548 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 549 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 550                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 551 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 552                                         BATU_VP)
 553 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 554 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 555
 556 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 557 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 558                                         BATL_MEMCOHERENCE)
 559 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 560                                         BATU_VS | BATU_VP)
 561 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 562                                         BATL_CACHEINHIBIT | \
 563                                         BATL_GUARDEDSTORAGE)
 564 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 565
 566 /* Stack in dcache: cacheable, no memory coherence */
 567 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 568 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 569                                         BATU_VS | BATU_VP)
 570 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 571 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 572
 573 /*
 574  * Environment Configuration
 575  */
 576
 577 #define CONFIG_ENV_OVERWRITE
 578
 579 #if defined(CONFIG_TSEC_ENET)
 580 #define CONFIG_HAS_ETH0
 581 #endif
 582
 583 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 584
 585
 586 #define CONFIG_HOSTNAME         hrcon
 587 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 588 #define CONFIG_BOOTFILE         "uImage"
 589
 590 #define CONFIG_PREBOOT          /* enable preboot variable */
 591
 592 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 593         "netdev=eth0\0"                                                 \
 594         "consoledev=ttyS1\0"                                            \
 595         "u-boot=u-boot.bin\0"                                           \
 596         "kernel_addr=1000000\0"                                 \
 597         "fdt_addr=C00000\0"                                             \
 598         "fdtfile=hrcon.dtb\0"                           \
 599         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 600         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 601                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 602                 " +${filesize};cp.b ${fileaddr} "                       \
 603                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 604         "upd=run load update\0"                                         \
 605
 606 #define CONFIG_NFSBOOTCOMMAND                                           \
 607         "setenv bootargs root=/dev/nfs rw "                             \
 608         "nfsroot=$serverip:$rootpath "                                  \
 609         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 610         "console=$consoledev,$baudrate $othbootargs;"                   \
 611         "tftp ${kernel_addr} $bootfile;"                                \
 612         "tftp ${fdt_addr} $fdtfile;"                                    \
 613         "bootm ${kernel_addr} - ${fdt_addr}"
 614
 615 #define CONFIG_MMCBOOTCOMMAND                                           \
 616         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 617         "console=$consoledev,$baudrate $othbootargs;"                   \
 618         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 619         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 620         "bootm ${kernel_addr} - ${fdt_addr}"
 621
 622 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 623
 624 #endif  /* __CONFIG_H */