3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_MPC830x 1 /* MPC830x family */
18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19 #define CONFIG_HRCON 1 /* HRCON board specific */
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
23 #define CONFIG_BOARD_EARLY_INIT_R
24 #define CONFIG_LAST_STAGE_INIT
26 #define CONFIG_FSL_ESDHC
27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
29 #define CONFIG_GENERIC_MMC
31 #define CONFIG_CMD_FPGAD
32 #define CONFIG_CMD_IOLOOP
37 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
38 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
41 * Hardware Reset Configuration Word
42 * if CLKIN is 66.66MHz, then
43 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
44 * We choose the A type silicon as default, so the core is 400Mhz.
46 #define CONFIG_SYS_HRCW_LOW (\
47 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
48 HRCWL_DDR_TO_SCB_CLK_2X1 |\
50 HRCWL_CSB_TO_CLKIN_4X1 |\
51 HRCWL_CORE_TO_CSB_3X1)
53 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
54 * in 8308's HRCWH according to the manual, but original Freescale's
55 * code has them and I've expirienced some problems using the board
56 * with BDI3000 attached when I've tried to set these bits to zero
57 * (UART doesn't work after the 'reset run' command).
59 #define CONFIG_SYS_HRCW_HIGH (\
61 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_FROM_0XFFF00100 |\
64 HRCWH_BOOTSEQ_DISABLE |\
65 HRCWH_SW_WATCHDOG_DISABLE |\
66 HRCWH_ROM_LOC_LOCAL_16BIT |\
67 HRCWH_RL_EXT_LEGACY |\
68 HRCWH_TSEC1M_IN_RGMII |\
69 HRCWH_TSEC2M_IN_RGMII |\
75 #define CONFIG_SYS_SICRH (\
81 SICRH_IEEE1588_A_GPIO |\
84 SICRH_IEEE1588_B_GPIO |\
89 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
90 #define CONFIG_SYS_SICRL (\
95 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
100 #define CONFIG_SYS_IMMR 0xE0000000
105 #define CONFIG_FSL_SERDES
106 #define CONFIG_FSL_SERDES1 0xe3000
111 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
112 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
113 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
118 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
120 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
121 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
122 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
129 * Manually set up DDR parameters
130 * consist of one chip NT5TU64M16HG from NANYA
133 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
135 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
136 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
137 | CSCONFIG_ODT_RD_NEVER \
138 | CSCONFIG_ODT_WR_ONLY_CURRENT \
139 | CSCONFIG_BANK_BIT_3 \
140 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
142 #define CONFIG_SYS_DDR_TIMING_3 0
143 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
144 | (0 << TIMING_CFG0_WRT_SHIFT) \
145 | (0 << TIMING_CFG0_RRT_SHIFT) \
146 | (0 << TIMING_CFG0_WWT_SHIFT) \
147 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
148 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
149 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
150 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
152 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
153 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
154 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
155 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
156 | (9 << TIMING_CFG1_REFREC_SHIFT) \
157 | (2 << TIMING_CFG1_WRREC_SHIFT) \
158 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
159 | (2 << TIMING_CFG1_WRTORD_SHIFT))
161 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
162 | (4 << TIMING_CFG2_CPO_SHIFT) \
163 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
164 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
165 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
166 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
167 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
169 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
170 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
172 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
173 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
177 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
178 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
179 | (0x0242 << SDRAM_MODE_SD_SHIFT))
180 /* ODT 150ohm CL=4, AL=0 on SDRAM */
181 #define CONFIG_SYS_DDR_MODE2 0x00000000
186 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
187 #define CONFIG_SYS_MEMTEST_END 0x07f00000
190 * The reserved memory
192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
194 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
195 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
198 * Initial RAM Base Address Setup
200 #define CONFIG_SYS_INIT_RAM_LOCK 1
201 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
203 #define CONFIG_SYS_GBL_DATA_OFFSET \
204 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
207 * Local Bus Configuration & Clock Setup
209 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
210 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
211 #define CONFIG_SYS_LBC_LBCR 0x00040000
214 * FLASH on the Local Bus
217 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
218 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
219 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
220 #define CONFIG_FLASH_CFI_LEGACY
221 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
223 #define CONFIG_SYS_NO_FLASH
226 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
227 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
228 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
230 /* Window base at flash base */
231 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
234 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
235 | BR_PS_16 /* 16 bit port */ \
236 | BR_MS_GPCM /* MSEL = GPCM */ \
238 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
247 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
248 #define CONFIG_SYS_MAX_FLASH_SECT 135
250 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
251 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
256 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
257 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
259 /* Window base at FPGA base */
260 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
261 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
263 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
264 | BR_PS_16 /* 16 bit port */ \
265 | BR_MS_GPCM /* MSEL = GPCM */ \
267 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
276 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
277 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
279 #define CONFIG_SYS_FPGA_COUNT 1
281 #define CONFIG_SYS_MCLINK_MAX 3
283 #define CONFIG_SYS_FPGA_PTR \
284 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
289 #define CONFIG_CONS_INDEX 2
290 #define CONFIG_SYS_NS16550_SERIAL
291 #define CONFIG_SYS_NS16550_REG_SIZE 1
292 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
294 #define CONFIG_SYS_BAUDRATE_TABLE \
295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
300 /* Pass open firmware flat tree */
303 #define CONFIG_SYS_I2C
304 #define CONFIG_SYS_I2C_FSL
305 #define CONFIG_SYS_FSL_I2C_SPEED 400000
306 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
307 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
309 #define CONFIG_PCA953X /* NXP PCA9554 */
310 #define CONFIG_PCA9698 /* NXP PCA9698 */
312 #define CONFIG_SYS_I2C_IHS
313 #define CONFIG_SYS_I2C_IHS_CH0
314 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
315 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
316 #define CONFIG_SYS_I2C_IHS_CH1
317 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
318 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
319 #define CONFIG_SYS_I2C_IHS_CH2
320 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
321 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
322 #define CONFIG_SYS_I2C_IHS_CH3
323 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
324 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
326 #ifdef CONFIG_HRCON_DH
327 #define CONFIG_SYS_I2C_IHS_DUAL
328 #define CONFIG_SYS_I2C_IHS_CH0_1
329 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
330 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
331 #define CONFIG_SYS_I2C_IHS_CH1_1
332 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
333 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
334 #define CONFIG_SYS_I2C_IHS_CH2_1
335 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
336 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
337 #define CONFIG_SYS_I2C_IHS_CH3_1
338 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
339 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
343 * Software (bit-bang) I2C driver configuration
345 #define CONFIG_SYS_I2C_SOFT
346 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
347 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
348 #define I2C_SOFT_DECLARATIONS2
349 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
350 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
351 #define I2C_SOFT_DECLARATIONS3
352 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
353 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
354 #define I2C_SOFT_DECLARATIONS4
355 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
356 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
357 #define I2C_SOFT_DECLARATIONS5
358 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
359 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
360 #define I2C_SOFT_DECLARATIONS6
361 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
362 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
363 #define I2C_SOFT_DECLARATIONS7
364 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
365 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
366 #define I2C_SOFT_DECLARATIONS8
367 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
368 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
370 #ifdef CONFIG_HRCON_DH
371 #define I2C_SOFT_DECLARATIONS9
372 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
373 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
374 #define I2C_SOFT_DECLARATIONS10
375 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
376 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
377 #define I2C_SOFT_DECLARATIONS11
378 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
379 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
380 #define I2C_SOFT_DECLARATIONS12
381 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
382 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
385 #ifdef CONFIG_HRCON_DH
386 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
387 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
388 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
391 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
392 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
393 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
398 void fpga_gpio_set(unsigned int bus, int pin);
399 void fpga_gpio_clear(unsigned int bus, int pin);
400 int fpga_gpio_get(unsigned int bus, int pin);
401 void fpga_control_set(unsigned int bus, int pin);
402 void fpga_control_clear(unsigned int bus, int pin);
405 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
406 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
407 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
409 #ifdef CONFIG_HRCON_DH
412 if (I2C_ADAP_HWNR > 7) \
413 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
415 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
418 #define I2C_ACTIVE { }
420 #define I2C_TRISTATE { }
422 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
423 #define I2C_SDA(bit) \
426 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
428 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
430 #define I2C_SCL(bit) \
433 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
435 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
437 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
440 * Software (bit-bang) MII driver configuration
442 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
443 #define CONFIG_BITBANGMII_MULTI
448 #define CONFIG_SYS_OSD_SCREENS 1
449 #define CONFIG_SYS_DP501_DIFFERENTIAL
450 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
452 #ifdef CONFIG_HRCON_DH
453 #define CONFIG_SYS_OSD_DH
458 * Addresses are mapped 1-1.
460 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
461 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
462 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
463 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
464 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
465 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
466 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
467 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
468 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
470 /* enable PCIE clock */
471 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
473 #define CONFIG_PCI_INDIRECT_BRIDGE
476 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
477 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
482 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
483 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
484 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
487 * TSEC ethernet configuration
489 #define CONFIG_MII 1 /* MII PHY management */
491 #define CONFIG_TSEC1_NAME "eTSEC0"
492 #define TSEC1_PHY_ADDR 1
493 #define TSEC1_PHYIDX 0
494 #define TSEC1_FLAGS TSEC_GIGABIT
496 /* Options are: eTSEC[0-1] */
497 #define CONFIG_ETHPRIME "eTSEC0"
503 #define CONFIG_ENV_IS_IN_FLASH 1
504 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
505 CONFIG_SYS_MONITOR_LEN)
506 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
507 #define CONFIG_ENV_SIZE 0x2000
508 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
509 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
511 #define CONFIG_ENV_IS_NOWHERE
512 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
515 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
516 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
519 * Command line configuration.
521 #define CONFIG_CMD_PCI
523 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
524 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
527 * Miscellaneous configurable options
529 #define CONFIG_SYS_LONGHELP /* undef to save memory */
530 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
531 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
533 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
535 /* Print Buffer Size */
536 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
537 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
538 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
541 * For booting Linux, the board info and command line data
542 * have to be in the first 256 MB of memory, since this is
543 * the maximum mapped by the Linux kernel during initialization.
545 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
550 #define CONFIG_SYS_HID0_INIT 0x000000000
551 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
552 HID0_ENABLE_INSTRUCTION_CACHE | \
553 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
554 #define CONFIG_SYS_HID2 HID2_HBE
560 /* DDR: cache cacheable */
561 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
563 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
565 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
566 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
568 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
569 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
570 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
571 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
573 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
574 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
576 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
577 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
579 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
581 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
582 BATL_CACHEINHIBIT | \
584 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
586 /* Stack in dcache: cacheable, no memory coherence */
587 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
588 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
590 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
591 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
594 * Environment Configuration
597 #define CONFIG_ENV_OVERWRITE
599 #if defined(CONFIG_TSEC_ENET)
600 #define CONFIG_HAS_ETH0
603 #define CONFIG_BAUDRATE 115200
605 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
608 #define CONFIG_HOSTNAME hrcon
609 #define CONFIG_ROOTPATH "/opt/nfsroot"
610 #define CONFIG_BOOTFILE "uImage"
612 #define CONFIG_PREBOOT /* enable preboot variable */
614 #define CONFIG_EXTRA_ENV_SETTINGS \
616 "consoledev=ttyS1\0" \
617 "u-boot=u-boot.bin\0" \
618 "kernel_addr=1000000\0" \
619 "fdt_addr=C00000\0" \
620 "fdtfile=hrcon.dtb\0" \
621 "load=tftp ${loadaddr} ${u-boot}\0" \
622 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
623 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
624 " +${filesize};cp.b ${fileaddr} " \
625 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
626 "upd=run load update\0" \
628 #define CONFIG_NFSBOOTCOMMAND \
629 "setenv bootargs root=/dev/nfs rw " \
630 "nfsroot=$serverip:$rootpath " \
631 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp ${kernel_addr} $bootfile;" \
634 "tftp ${fdt_addr} $fdtfile;" \
635 "bootm ${kernel_addr} - ${fdt_addr}"
637 #define CONFIG_MMCBOOTCOMMAND \
638 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
639 "console=$consoledev,$baudrate $othbootargs;" \
640 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
641 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
642 "bootm ${kernel_addr} - ${fdt_addr}"
644 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
646 #endif /* __CONFIG_H */