3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Hymod board
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_HYMOD 1 /* ...on a Hymod board */
39 #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
42 * select serial console configuration
44 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 * if CONFIG_CONS_NONE is defined, then the serial console routines must
49 * defined elsewhere (for example, on the cogent platform, there are serial
50 * ports on the motherboard which are used for the serial console - see
51 * cogent/cma101/serial.[ch]).
53 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
54 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
55 #undef CONFIG_CONS_NONE /* define if console on something else*/
56 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
57 #define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
58 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
59 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
62 * select ethernet configuration
64 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
65 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
68 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
69 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
70 * from CONFIG_COMMANDS to remove support for networking.
72 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
73 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
74 #undef CONFIG_ETHER_NONE /* define if ether on something else */
75 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */
77 #if (CONFIG_ETHER_INDEX == 1)
82 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
83 * - Enable Full Duplex in FSMR
85 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
86 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
87 # define CFG_CPMFCR_RAMTYPE 0
88 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
90 #elif (CONFIG_ETHER_INDEX == 2)
95 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
96 * - Enable Full Duplex in FSMR
98 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
99 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
100 # define CFG_CPMFCR_RAMTYPE 0
101 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
103 #elif (CONFIG_ETHER_INDEX == 3)
108 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
109 * - Enable Full Duplex in FSMR
111 # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
112 # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
113 # define CFG_CPMFCR_RAMTYPE 0
114 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
116 #endif /* CONFIG_ETHER_INDEX */
120 #define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
122 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
124 #define CONFIG_8260_CLKIN 33333333 /* in Hz */
126 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
129 #if defined(CONFIG_CONS_USE_EXTC)
130 #define CONFIG_BAUDRATE 115200
132 #define CONFIG_BAUDRATE 38400
135 /* default ip addresses - these will be overridden */
136 #define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
137 #define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
139 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
159 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
160 #include <cmd_confdefs.h>
163 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
166 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
167 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
168 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
169 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
170 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
171 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
172 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
173 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
174 # if defined(CONFIG_KGDB_USE_EXTC)
175 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
177 #define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port at */
181 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
183 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
186 * Hymod specific configurable options
188 #undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */
191 * Miscellaneous configurable options
193 #define CFG_LONGHELP /* undef to save memory */
194 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
195 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
196 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
198 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
200 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
201 #define CFG_MAXARGS 16 /* max number of command args */
202 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
204 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
205 #define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
207 #define CFG_LOAD_ADDR 0x100000 /* default load address */
209 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
211 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
213 #define CFG_I2C_SPEED 50000
214 #define CFG_I2C_SLAVE 0x7e
216 /* these are for the ST M24C02 2kbit serial i2c eeprom */
217 #define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
218 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
219 #define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
222 * Low Level Configuration Settings
223 * (address mappings, register initial values, etc.)
224 * You should know what you are doing if you make changes here.
227 /*-----------------------------------------------------------------------
228 * Hard Reset Configuration Words
230 * if you change bits in the HRCW, you must also change the CFG_*
231 * defines for the various registers affected by the HRCW e.g. changing
232 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
235 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
236 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
239 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
240 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
243 /* no slaves so just duplicate the master hrcw */
244 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
245 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
246 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
247 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
248 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
249 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
250 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
252 /*-----------------------------------------------------------------------
253 * Internal Memory Mapped Register
255 #define CFG_IMMR 0xF0000000
257 /*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in DPRAM)
260 #define CFG_INIT_RAM_ADDR CFG_IMMR
261 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
262 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
263 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
264 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
266 /*-----------------------------------------------------------------------
267 * Start addresses for the final memory configuration
268 * (Set up by the startup code)
269 * Please note that CFG_SDRAM_BASE _must_ start at 0
271 #define CFG_SDRAM_BASE 0x00000000
272 #define CFG_FLASH_BASE TEXT_BASE
273 #define CFG_MONITOR_BASE TEXT_BASE
274 #define CFG_FPGA_BASE 0x80000000
276 * unfortunately, CFG_MONITOR_LEN must include the
277 * (very large i.e. 256kB) environment flash sector
279 #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
280 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
283 * For booting Linux, the board info and command line data
284 * have to be in the first 8 MB of memory, since this is
285 * the maximum mapped by the Linux kernel during initialization.
287 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
289 /*-----------------------------------------------------------------------
292 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
293 #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
295 #define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
296 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
298 #define CFG_FLASH_TYPE FLASH_28F640J3A
299 #define CFG_FLASH_ID (INTEL_ID_28F640J3A & 0xff)
300 #define CFG_FLASH_NBLOCKS 64
302 #define CFG_ENV_IS_IN_FLASH 1
303 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
304 #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
305 #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
307 /*-----------------------------------------------------------------------
308 * Cache Configuration
310 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
311 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
312 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
315 /*-----------------------------------------------------------------------
316 * HIDx - Hardware Implementation-dependent Registers 2-11
317 *-----------------------------------------------------------------------
318 * HID0 also contains cache control - initially enable both caches and
319 * invalidate contents, then the final state leaves only the instruction
320 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
321 * but Soft reset does not.
323 * HID1 has only read-only information - nothing to set.
325 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
328 #define CFG_HID0_FINAL 0
330 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
334 /*-----------------------------------------------------------------------
335 * RMR - Reset Mode Register 5-5
336 *-----------------------------------------------------------------------
337 * turn on Checkstop Reset Enable
342 #define CFG_RMR RMR_CSRE
345 /*-----------------------------------------------------------------------
346 * BCR - Bus Configuration 4-25
347 *-----------------------------------------------------------------------
349 #define CFG_BCR (BCR_ETM)
351 /*-----------------------------------------------------------------------
352 * SIUMCR - SIU Module Configuration 4-31
353 *-----------------------------------------------------------------------
355 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
356 SIUMCR_APPC10|SIUMCR_MMR11)
358 /*-----------------------------------------------------------------------
359 * SYPCR - System Protection Control 4-35
360 * SYPCR can only be written once after reset!
361 *-----------------------------------------------------------------------
362 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
364 #if defined(CONFIG_WATCHDOG)
365 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
366 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
368 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
369 SYPCR_SWRI|SYPCR_SWP)
370 #endif /* CONFIG_WATCHDOG */
372 /*-----------------------------------------------------------------------
373 * TMCNTSC - Time Counter Status and Control 4-40
374 *-----------------------------------------------------------------------
375 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
376 * and enable Time Counter
378 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
380 /*-----------------------------------------------------------------------
381 * PISCR - Periodic Interrupt Status and Control 4-42
382 *-----------------------------------------------------------------------
383 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
386 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
388 /*-----------------------------------------------------------------------
389 * SCCR - System Clock Control 9-8
390 *-----------------------------------------------------------------------
391 * Ensure DFBRG is Divide by 16
393 #define CFG_SCCR (SCCR_DFBRG01)
395 /*-----------------------------------------------------------------------
396 * RCCR - RISC Controller Configuration 13-7
397 *-----------------------------------------------------------------------
402 * Init Memory Controller:
404 * Bank Bus Machine PortSz Device
405 * ---- --- ------- ------ ------
406 * 0 60x GPCM 32 bit FLASH
407 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
408 * 2 60x SDRAM 64 bit SDRAM
409 * 3 Local UPMC 8 bit Main Xilinx configuration
410 * 4 Local GPCM 32 bit Main Xilinx register mode
411 * 5 Local UPMB 32 bit Main Xilinx port mode
412 * 6 Local UPMC 8 bit Mezz Xilinx configuration
418 * Quotes from the HYMOD IO Board Reference manual:
420 * "The flash memory is two Intel StrataFlash chips, each configured for
421 * 16 bit operation and connected to give a 32 bit wide port."
423 * "The chip select logic is configured to respond to both *CS0 and *CS1.
424 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
425 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
426 * FLASH will then appear as ROM during boot."
428 * Initially, we are only going to use bank 0 in read/write mode.
431 /* 32 bit, read-write, GPCM on 60x bus */
432 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\
433 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
435 #define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
440 * Quotes from the HYMOD IO Board Reference manual:
442 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
443 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
444 * dynamic random access memory organised as 4 banks by 4096 rows by 512
445 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
447 * "The locations in SDRAM are accessed using multiplexed address pins to
448 * specify row and column. The pins also act to specify commands. The state
449 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
450 * pin may function as a row address or as the AUTO PRECHARGE control line,
451 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
452 * address lines to be configured to the required multiplexing scheme."
455 #define CFG_SDRAM_SIZE 64
457 /* 64 bit, read-write, SDRAM on 60x bus */
458 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
459 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
460 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
461 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\
462 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
465 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
467 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
468 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
469 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
470 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
471 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
472 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
473 * command is 2 clocks, earliest timing for PRECHARGE after last data
474 * was read is 1 clock, earliest timing for PRECHARGE after last data
475 * was written is 1 clock, CAS Latency is 2.
478 #define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
479 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
480 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
481 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
482 PSDMR_WRC_1C|PSDMR_CL_2)
485 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
486 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
487 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
488 * Prescaler, hence the P instead of the R). The refresh timer period is given
489 * by (note that there was a change in the 8260 UM Errata):
491 * TimerPeriod = (PSRT + 1) / Fmptc
493 * where Fmptc is the BusClock divided by PTP. i.e.
495 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
499 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
501 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
502 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
505 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
506 * appear to be reasonable.
511 #define CFG_MPTPR MPTPR_PTP_DIV8
514 #define CFG_MPTPR MPTPR_PTP_DIV32
518 * Banks 3,4,5 and 6 - FPGA access
520 * Quotes from the HYMOD IO Board Reference manual:
522 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
523 * for configuring an optional FPGA on the mezzanine interface.
525 * Access to the FPGAs may be divided into several catagories:
528 * 2. Register mode access
529 * 3. Port mode access
531 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
532 * configured only (mode 1). Consequently there are four access types.
534 * To improve interface performance and simplify software design, the four
535 * possible access types are separately mapped to different memory banks.
537 * All are accessed using the local bus."
539 * Device Mode Memory Bank Machine Port Size Access
541 * Main Configuration 3 UPMC 8bit R/W
542 * Main Register 4 GPCM 32bit R/W
543 * Main Port 5 UPMB 32bit R/W
544 * Mezzanine Configuration 6 UPMC 8bit W/O
546 * "Note that mezzanine mode 1 access is write-only."
549 /* all the bank sizes must be a power of two, greater or equal to 32768 */
550 #define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
551 #define FPGA_MAIN_CFG_SIZE 32768
552 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
553 #define FPGA_MAIN_REG_SIZE 32768
554 #define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
555 #define FPGA_MAIN_PORT_SIZE 32768
556 #define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
557 #define FPGA_MEZZ_CFG_SIZE 32768
559 /* 8 bit, read-write, UPMC */
560 #define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
561 /* up to 32Kbyte, burst inhibit */
562 #define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
564 /* 32 bit, read-write, GPCM */
565 #define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
567 #define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
569 /* 32 bit, read-write, UPMB */
570 #define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
572 #define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
574 /* 8 bit, write-only, UPMC */
575 #define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
576 /* up to 32Kbyte, burst inhibit */
577 #define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
579 /*-----------------------------------------------------------------------
580 * MBMR - Machine B Mode 10-27
581 *-----------------------------------------------------------------------
583 #define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
585 /*-----------------------------------------------------------------------
586 * MCMR - Machine C Mode 10-27
587 *-----------------------------------------------------------------------
589 #define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
592 * FPGA I/O Port/Bit information
595 #define FPGA_MAIN_PROG_PORT IOPIN_PORTA
596 #define FPGA_MAIN_PROG_PIN 4 /* PA4 */
597 #define FPGA_MAIN_INIT_PORT IOPIN_PORTA
598 #define FPGA_MAIN_INIT_PIN 5 /* PA5 */
599 #define FPGA_MAIN_DONE_PORT IOPIN_PORTA
600 #define FPGA_MAIN_DONE_PIN 6 /* PA6 */
602 #define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
603 #define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
604 #define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
605 #define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
606 #define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
607 #define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
608 #define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
609 #define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
612 * Internal Definitions
616 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
617 #define BOOTFLAG_WARM 0x02 /* Software reboot */
619 #endif /* __CONFIG_H */