3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * Sergej Stepanov <ste@ids.de>
9 * SPDX-License-Identifier: GPL-2.0+
16 * High Level Configuration Options
18 #define CONFIG_MPC831x
19 #define CONFIG_MPC8313
20 #define CONFIG_IDS8313
22 #define CONFIG_SYS_GENERIC_BOARD
24 #define CONFIG_FSL_ELBC
26 #define CONFIG_MISC_INIT_R
28 #define CONFIG_BOOT_RETRY_TIME 900
29 #define CONFIG_BOOT_RETRY_MIN 30
30 #define CONFIG_BOOTDELAY 1
31 #define CONFIG_RESET_TO_RETRY
33 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
34 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
36 #define CONFIG_SYS_IMMR 0xF0000000
38 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
39 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
42 * Hardware Reset Configuration Word
43 * if CLKIN is 66.000MHz, then
44 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
46 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
47 HRCWL_DDR_TO_SCB_CLK_2X1 |\
48 HRCWL_CSB_TO_CLKIN_2X1 |\
49 HRCWL_CORE_TO_CSB_2X1)
51 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
53 HRCWH_FROM_0XFFF00100 |\
54 HRCWH_BOOTSEQ_DISABLE |\
55 HRCWH_SW_WATCHDOG_DISABLE |\
56 HRCWH_ROM_LOC_LOCAL_8BIT |\
57 HRCWH_RL_EXT_LEGACY |\
58 HRCWH_TSEC1M_IN_MII |\
59 HRCWH_TSEC2M_IN_MII |\
62 #define CONFIG_SYS_SICRH 0x00000000
63 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
65 #define CONFIG_HWCONFIG
67 #define CONFIG_SYS_HID0_INIT 0x000000000
68 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
69 HID0_ENABLE_INSTRUCTION_CACHE |\
70 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
72 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
75 * Definitions for initial stack pointer and data area (in DCACHE )
77 #define CONFIG_SYS_INIT_RAM_LOCK
78 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
79 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
80 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
81 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
82 - CONFIG_SYS_GBL_DATA_SIZE)
83 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86 * Local Bus LCRR and LBCR regs
88 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
89 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
90 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\
91 (0xFF << LBCR_BMT_SHIFT) |\
94 #define CONFIG_SYS_LBC_MRTPR 0x20000000
97 * Internal Definitions
102 #define CONFIG_SYS_DDR_BASE 0x00000000
103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
104 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
107 * Manually set up DDR parameters,
108 * as this board has not the SPD connected to I2C.
110 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
111 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
113 CSCONFIG_ROW_BIT_13 |\
116 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
119 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
120 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
121 (3 << TIMING_CFG0_WRT_SHIFT) |\
122 (3 << TIMING_CFG0_RRT_SHIFT) |\
123 (3 << TIMING_CFG0_WWT_SHIFT) |\
124 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
125 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
126 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
127 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
128 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
129 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
130 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
131 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
132 (4 << TIMING_CFG1_REFREC_SHIFT) |\
133 (4 << TIMING_CFG1_WRREC_SHIFT) |\
134 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
135 (2 << TIMING_CFG1_WRTORD_SHIFT))
136 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
137 (5 << TIMING_CFG2_CPO_SHIFT) |\
138 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
139 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
140 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
141 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
142 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
144 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
145 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
147 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
148 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
150 SDRAM_CFG_SDRAM_TYPE_DDR2)
152 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
153 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
154 (0x0242 << SDRAM_MODE_SD_SHIFT))
155 #define CONFIG_SYS_DDR_MODE_2 0x00000000
156 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
157 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
169 #define CONFIG_TSEC_ENET
170 #define CONFIG_HARD_SPI
171 #define CONFIG_HARD_I2C
176 #define CONFIG_SYS_FLASH_CFI
177 #define CONFIG_FLASH_CFI_DRIVER
178 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
179 #define CONFIG_FLASH_SHOW_PROGRESS 50
180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
182 #define CONFIG_SYS_FLASH_BASE 0xFF800000
183 #define CONFIG_SYS_FLASH_SIZE 8
184 #define CONFIG_SYS_FLASH_PROTECTION
186 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
187 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
189 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
194 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
200 #define CONFIG_SYS_MAX_FLASH_BANKS 1
201 #define CONFIG_SYS_MAX_FLASH_SECT 128
203 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
204 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
209 #define CONFIG_SYS_NAND_BASE 0xE1000000
210 #define CONFIG_SYS_MAX_NAND_DEVICE 1
211 #define CONFIG_SYS_NAND_MAX_CHIPS 1
212 #define CONFIG_NAND_FSL_ELBC
213 #define CONFIG_SYS_NAND_PAGE_SIZE (2048)
214 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
215 #define NAND_CACHE_PAGES 64
217 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
218 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
219 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
220 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
222 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
223 (2<<BR_DECC_SHIFT) |\
228 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
241 #define CONFIG_SYS_MRAM_BASE 0xE2000000
242 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
243 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
244 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
246 #define CONFIG_SYS_OR_TIMING_MRAM
248 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
253 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
258 #define CONFIG_SYS_CPLD_BASE 0xE3000000
259 #define CONFIG_SYS_CPLD_SIZE 0x8000
260 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
261 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
263 #define CONFIG_SYS_OR_TIMING_MRAM
265 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
270 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
275 #define CONFIG_WATCHDOG 1
276 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
281 #define CONFIG_CMD_I2C
282 #define CONFIG_SYS_I2C
283 #define CONFIG_SYS_I2C_FSL
284 #define CONFIG_SYS_FSL_I2C_SPEED 400000
285 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
286 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
287 #define CONFIG_RTC_PCF8563
288 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
293 #ifdef CONFIG_HARD_SPI
294 #define CONFIG_MPC8XXX_SPI
295 #define CONFIG_CMD_SPI
296 #define CONFIG_SYS_GPIO1_PRELIM
297 #define CONFIG_SYS_GPIO1_DIR 0x00000001
298 #define CONFIG_SYS_GPIO1_DAT 0x00000001
305 #define CONFIG_HAS_ETH0
306 #define CONFIG_TSEC1_NAME "TSEC0"
307 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
308 #define TSEC1_PHY_ADDR 0x1
309 #define TSEC1_FLAGS TSEC_GIGABIT
310 #define TSEC1_PHYIDX 0
314 #define CONFIG_HAS_ETH1
315 #define CONFIG_TSEC2_NAME "TSEC1"
316 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
317 #define TSEC2_PHY_ADDR 0x3
318 #define TSEC2_FLAGS TSEC_GIGABIT
319 #define TSEC2_PHYIDX 0
321 #define CONFIG_ETHPRIME "TSEC1"
326 #define CONFIG_CONS_INDEX 1
327 #define CONFIG_SYS_NS16550
328 #define CONFIG_SYS_NS16550_SERIAL
329 #define CONFIG_SYS_NS16550_REG_SIZE 1
331 #define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
335 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
337 #define CONFIG_HAS_FSL_DR_USB
338 #define CONFIG_SYS_SCCR_USBDRCM 3
343 #define CONFIG_HIGH_BATS
345 /* DDR @ 0x00000000 */
346 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
348 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
352 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
353 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
355 /* Initial RAM @ 0xFD000000 */
356 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
359 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
363 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
364 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
366 /* FLASH @ 0xFF800000 */
367 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
370 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
374 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
378 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
380 #define CONFIG_SYS_IBAT3L (0)
381 #define CONFIG_SYS_IBAT3U (0)
382 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
383 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
385 #define CONFIG_SYS_IBAT4L (0)
386 #define CONFIG_SYS_IBAT4U (0)
387 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
388 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
390 /* IMMRBAR @ 0xF0000000 */
391 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
395 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
399 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
400 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
402 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
403 #define CONFIG_SYS_IBAT6L (0xE0000000 |\
406 #define CONFIG_SYS_IBAT6U (0xE0000000 |\
410 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
411 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
413 #define CONFIG_SYS_IBAT7L (0)
414 #define CONFIG_SYS_IBAT7U (0)
415 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
416 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
419 * U-Boot environment setup
421 #include <config_cmd_default.h>
423 #define CONFIG_CMD_DHCP
424 #define CONFIG_CMD_PING
425 #define CONFIG_CMD_NFS
426 #define CONFIG_CMD_NAND
427 #define CONFIG_CMD_FLASH
428 #define CONFIG_CMD_SNTP
429 #define CONFIG_CMD_MII
430 #define CONFIG_CMD_DATE
431 #define CONFIG_CMDLINE_EDITING
432 #define CONFIG_CMD_EDITENV
433 #define CONFIG_CMD_JFFS2
434 #define CONFIG_BOOTP_SUBNETMASK
435 #define CONFIG_BOOTP_GATEWAY
436 #define CONFIG_BOOTP_HOSTNAME
437 #define CONFIG_BOOTP_BOOTPATH
438 #define CONFIG_BOOTP_BOOTFILESIZE
439 /* pass open firmware flat tree */
440 #define CONFIG_OF_LIBFDT
441 #define CONFIG_OF_BOARD_SETUP
442 #define CONFIG_OF_STDOUT_VIA_ALIAS
445 * The reserved memory
447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
448 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
449 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
452 * Environment Configuration
454 #define CONFIG_ENV_IS_IN_FLASH
455 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
456 + CONFIG_SYS_MONITOR_LEN)
457 #define CONFIG_ENV_SIZE 0x20000
458 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
459 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
462 #define CONFIG_NETDEV eth1
463 #define CONFIG_HOSTNAME ids8313
464 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
465 #define CONFIG_BOOTFILE "ids8313/uImage"
466 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
467 #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
468 #define CONFIG_LOADADDR 0x400000
469 #define CONFIG_CMD_ENV_FLAGS
470 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
472 #define CONFIG_BAUDRATE 115200
474 /* Initial Memory map for Linux*/
475 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
478 * Miscellaneous configurable options
480 #define CONFIG_SYS_LONGHELP
481 #define CONFIG_SYS_CBSIZE 1024
482 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
483 + sizeof(CONFIG_SYS_PROMPT)+16)
484 #define CONFIG_SYS_MAXARGS 16
485 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
486 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
487 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
489 #define CONFIG_SYS_MEMTEST_START 0x00001000
490 #define CONFIG_SYS_MEMTEST_END 0x00C00000
492 #define CONFIG_SYS_LOAD_ADDR 0x100000
494 #define CONFIG_LOADS_ECHO
495 #define CONFIG_TIMESTAMP
496 #define CONFIG_PREBOOT "echo;" \
497 "echo Type \\\"run nfsboot\\\" " \
498 "to mount root filesystem over NFS;echo"
499 #undef CONFIG_BOOTARGS
500 #define CONFIG_BOOTCOMMAND "run boot_cramfs"
501 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
503 #define CONFIG_JFFS2_NAND
504 #define CONFIG_JFFS2_DEV "0"
506 /* mtdparts command line support */
507 #define CONFIG_CMD_MTDPARTS
508 #define CONFIG_FLASH_CFI_MTD
509 #define CONFIG_MTD_DEVICE
510 #define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash"
511 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \
513 "128k(BOOT-ENV),128k(BOOT-REDENV);" \
514 "e1000000.flash:-(ubi)"
516 #define CONFIG_EXTRA_ENV_SETTINGS \
517 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
519 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
520 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
521 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
523 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
525 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
527 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
529 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
532 "fdtaddr=0x780000\0" \
533 "kernel_addr=ff800000\0" \
534 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
535 "setbootargs=setenv bootargs " \
536 "root=${rootdev} rw console=${console}," \
537 "${baudrate} ${othbootargs}\0" \
538 "setipargs=setenv bootargs root=${rootdev} rw " \
539 "nfsroot=${serverip}:${rootpath} " \
540 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
541 "${netmask}:${hostname}:${netdev}:off " \
542 "console=${console},${baudrate} ${othbootargs}\0" \
543 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
544 "mtdids=" MTDIDS_DEFAULT "\0" \
545 "mtdparts=" MTDPARTS_DEFAULT "\0" \
548 #define CONFIG_NFSBOOTCOMMAND \
549 "setenv rootdev /dev/nfs;" \
550 "run setipargs;run addmtd;" \
551 "tftp ${loadaddr} ${bootfile};" \
552 "tftp ${fdtaddr} ${fdtfile};" \
553 "fdt addr ${fdtaddr};" \
554 "bootm ${loadaddr} - ${fdtaddr}"
557 #define CONFIG_CMD_NAND_TRIMFFS
558 #define CONFIG_CMD_UBI
559 #define CONFIG_CMD_UBIFS
560 #define CONFIG_RBTREE
562 #define CONFIG_MTD_PARTITIONS
564 /* bootcount support */
565 #define CONFIG_BOOTCOUNT_LIMIT
566 #define CONFIG_BOOTCOUNT_I2C
567 #define CONFIG_BOOTCOUNT_ALEN 1
568 #define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
570 #define CONFIG_VERSION_VARIABLE
572 #define CONFIG_IMAGE_FORMAT_LEGACY
573 #define CONFIG_CMD_FDT
574 #define CONFIG_CMD_HASH
576 #define CONFIG_SHA256
578 #endif /* __CONFIG_H */