2 * Common configuration settings for IGEP technology based boards
5 * ISEE 2007 SL, <www.iseebcn.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sizes.h>
29 * High Level Configuration Options
31 #define CONFIG_OMAP 1 /* in a TI OMAP core */
32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
33 #define CONFIG_OMAP_GPIO
35 #define CONFIG_SDRC /* The chip has SDRC controller */
37 #include <asm/arch/cpu.h>
38 #include <asm/arch/omap3.h>
41 * Display CPU and Board information
43 #define CONFIG_DISPLAY_CPUINFO 1
44 #define CONFIG_DISPLAY_BOARDINFO 1
47 #define V_OSCK 26000000 /* Clock output from T2 */
48 #define V_SCLK (V_OSCK >> 1)
50 #define CONFIG_MISC_INIT_R
52 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53 #define CONFIG_SETUP_MEMORY_TAGS 1
54 #define CONFIG_INITRD_TAG 1
55 #define CONFIG_REVISION_TAG 1
57 #define CONFIG_OF_LIBFDT 1
60 * NS16550 Configuration
63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
65 #define CONFIG_SYS_NS16550
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
70 /* define to avoid U-Boot to hang while waiting for TEMT */
71 #define CONFIG_SYS_NS16550_BROKEN_TEMT
73 /* select serial console configuration */
74 #define CONFIG_CONS_INDEX 3
75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
76 #define CONFIG_SERIAL3 3
78 /* allow to overwrite serial and ethaddr */
79 #define CONFIG_ENV_OVERWRITE
80 #define CONFIG_BAUDRATE 115200
81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
83 #define CONFIG_GENERIC_MMC 1
85 #define CONFIG_OMAP_HSMMC 1
86 #define CONFIG_DOS_PARTITION 1
89 #define CONFIG_MUSB_UDC 1
90 #define CONFIG_USB_OMAP3 1
91 #define CONFIG_TWL4030_USB 1
93 /* USB device configuration */
94 #define CONFIG_USB_DEVICE 1
95 #define CONFIG_USB_TTY 1
96 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
98 /* Change these to suit your needs */
99 #define CONFIG_USBD_VENDORID 0x0451
100 #define CONFIG_USBD_PRODUCTID 0x5678
101 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
102 #define CONFIG_USBD_PRODUCT_NAME "IGEP"
104 /* commands to include */
105 #include <config_cmd_default.h>
107 #define CONFIG_CMD_CACHE
108 #define CONFIG_CMD_EXT2 /* EXT2 Support */
109 #define CONFIG_CMD_FAT /* FAT support */
110 #define CONFIG_CMD_I2C /* I2C serial bus support */
111 #define CONFIG_CMD_MMC /* MMC support */
112 #ifdef CONFIG_BOOT_ONENAND
113 #define CONFIG_CMD_ONENAND /* ONENAND support */
115 #ifdef CONFIG_BOOT_NAND
116 #define CONFIG_CMD_NAND
118 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
119 #define CONFIG_CMD_DHCP
120 #define CONFIG_CMD_PING
121 #define CONFIG_CMD_NFS /* NFS support */
122 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
123 #define CONFIG_MTD_DEVICE
125 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
126 #undef CONFIG_CMD_IMLS /* List all found images */
128 #define CONFIG_SYS_NO_FLASH
129 #define CONFIG_HARD_I2C 1
130 #define CONFIG_SYS_I2C_SPEED 100000
131 #define CONFIG_SYS_I2C_SLAVE 1
132 #define CONFIG_DRIVER_OMAP34XX_I2C 1
137 #define CONFIG_TWL4030_POWER 1
139 #define CONFIG_BOOTDELAY 3
141 #define CONFIG_EXTRA_ENV_SETTINGS \
143 "loadaddr=0x82000000\0" \
145 "console=ttyO2,115200n8\0" \
148 "dvimode=1024x768MR-16@60\0" \
149 "defaultdisplay=dvi\0" \
151 "mmcroot=/dev/mmcblk0p2 rw\0" \
152 "mmcrootfstype=ext4 rootwait\0" \
153 "nandroot=/dev/mtdblock4 rw\0" \
154 "nandrootfstype=jffs2\0" \
155 "mmcargs=setenv bootargs console=${console} " \
156 "mpurate=${mpurate} " \
158 "omapfb.mode=dvi:${dvimode} " \
160 "omapdss.def_disp=${defaultdisplay} " \
162 "rootfstype=${mmcrootfstype}\0" \
163 "nandargs=setenv bootargs console=${console} " \
164 "mpurate=${mpurate} " \
166 "omapfb.mode=dvi:${dvimode} " \
168 "omapdss.def_disp=${defaultdisplay} " \
169 "root=${nandroot} " \
170 "rootfstype=${nandrootfstype}\0" \
171 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
172 "importbootenv=echo Importing environment from mmc ...; " \
173 "env import -t $loadaddr $filesize\0" \
174 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
175 "mmcboot=echo Booting from mmc ...; " \
177 "bootm ${loadaddr}\0" \
178 "nandboot=echo Booting from onenand ...; " \
180 "onenand read ${loadaddr} 280000 400000; " \
181 "bootm ${loadaddr}\0" \
183 #define CONFIG_BOOTCOMMAND \
184 "mmc dev ${mmcdev}; if mmc rescan; then " \
185 "echo SD/MMC found on device ${mmcdev};" \
186 "if run loadbootenv; then " \
187 "run importbootenv;" \
189 "if test -n $uenvcmd; then " \
190 "echo Running uenvcmd ...;" \
193 "if run loaduimage; then " \
199 #define CONFIG_AUTO_COMPLETE 1
202 * Miscellaneous configurable options
204 #define CONFIG_SYS_LONGHELP /* undef to save memory */
205 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
206 #define CONFIG_SYS_PROMPT "U-Boot # "
207 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
208 /* Print Buffer Size */
209 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
210 sizeof(CONFIG_SYS_PROMPT) + 16)
211 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
212 /* Boot Argument Buffer Size */
213 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
215 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
217 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
218 0x01F00000) /* 31MB */
220 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
223 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
226 * OMAP3 has 12 GP timers, they can be driven by the system clock
227 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
228 * This rate is divided by a local divisor.
230 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
231 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
232 #define CONFIG_SYS_HZ 1000
235 * Physical Memory Map
238 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
239 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
240 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
243 * FLASH and environment organization
246 #ifdef CONFIG_BOOT_ONENAND
247 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
249 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
251 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
253 #define CONFIG_ENV_IS_IN_ONENAND 1
254 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
255 #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
258 #ifdef CONFIG_BOOT_NAND
259 #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
260 #define CONFIG_NAND_OMAP_GPMC
261 #define CONFIG_SYS_NAND_BASE NAND_BASE
262 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
263 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
264 #define CONFIG_ENV_IS_IN_NAND 1
265 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
266 #define CONFIG_ENV_ADDR NAND_ENV_OFFSET
267 #define CONFIG_SYS_MAX_NAND_DEVICE 1
271 * Size of malloc() pool
273 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
278 #if defined(CONFIG_CMD_NET)
279 #define CONFIG_SMC911X
280 #define CONFIG_SMC911X_32_BIT
281 #define CONFIG_SMC911X_BASE 0x2C000000
282 #endif /* (CONFIG_CMD_NET) */
285 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
286 * and older u-boot.bin with the new U-Boot SPL.
288 #define CONFIG_SYS_TEXT_BASE 0x80008000
289 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
290 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
291 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
292 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
293 CONFIG_SYS_INIT_RAM_SIZE - \
294 GENERATED_GBL_DATA_SIZE)
298 #define CONFIG_SPL_FRAMEWORK
299 #define CONFIG_SPL_NAND_SIMPLE
300 #define CONFIG_SPL_TEXT_BASE 0x40200800
301 #define CONFIG_SPL_MAX_SIZE (54 * 1024)
302 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
304 /* move malloc and bss high to prevent clashing with the main image */
305 #define CONFIG_SYS_SPL_MALLOC_START 0x87000000
306 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
307 #define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
308 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
310 /* MMC boot config */
311 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
312 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
313 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
314 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
316 #define CONFIG_SPL_BOARD_INIT
317 #define CONFIG_SPL_LIBCOMMON_SUPPORT
318 #define CONFIG_SPL_LIBDISK_SUPPORT
319 #define CONFIG_SPL_I2C_SUPPORT
320 #define CONFIG_SPL_LIBGENERIC_SUPPORT
321 #define CONFIG_SPL_MMC_SUPPORT
322 #define CONFIG_SPL_FAT_SUPPORT
323 #define CONFIG_SPL_SERIAL_SUPPORT
325 #define CONFIG_SPL_POWER_SUPPORT
326 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
328 #ifdef CONFIG_BOOT_ONENAND
329 #define CONFIG_SPL_ONENAND_SUPPORT
331 /* OneNAND boot config */
332 #define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
333 #define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
334 #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
335 #define CONFIG_SPL_ONENAND_LOAD_SIZE \
336 (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
340 #ifdef CONFIG_BOOT_NAND
341 #define CONFIG_SPL_NAND_SUPPORT
342 #define CONFIG_SPL_NAND_BASE
343 #define CONFIG_SPL_NAND_DRIVERS
344 #define CONFIG_SPL_NAND_ECC
346 /* NAND boot config */
347 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
348 #define CONFIG_SYS_NAND_PAGE_COUNT 64
349 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
350 #define CONFIG_SYS_NAND_OOBSIZE 64
351 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
352 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
353 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
355 #define CONFIG_SYS_NAND_ECCSIZE 512
356 #define CONFIG_SYS_NAND_ECCBYTES 3
357 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
358 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
361 #endif /* __IGEP00X0_H */