2 * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
5 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef __IMX27LITE_COMMON_CONFIG_H
24 #define __IMX27LITE_COMMON_CONFIG_H
29 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
31 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
32 #define CONFIG_SYS_HZ 1000
34 #define CONFIG_DISPLAY_BOARDINFO
35 #define CONFIG_DISPLAY_CPUINFO
37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS 1
39 #define CONFIG_INITRD_TAG 1
42 * Lowlevel configuration
44 #define SDRAM_ESDCFG_REGISTER_VAL(cas) \
55 #define SDRAM_ESDCTL_REGISTER_VAL \
65 #define SDRAM_ALL_VAL 0xf00
67 #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
68 #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
70 #define MPCTL0_VAL 0x1ef15d5
72 #define SPCTL0_VAL 0x043a1c09
74 #define CSCR_VAL 0x33f08107
76 #define PCDR0_VAL 0x120470c3
77 #define PCDR1_VAL 0x03030303
78 #define PCCR0_VAL 0xffffffff
79 #define PCCR1_VAL 0xfffffffc
81 #define AIPI1_PSR0_VAL 0x20040304
82 #define AIPI1_PSR1_VAL 0xdffbfcfb
83 #define AIPI2_PSR0_VAL 0x07ffc200
84 #define AIPI2_PSR1_VAL 0xffffffff
90 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024)
91 /* memtest start address */
92 #define CONFIG_SYS_MEMTEST_START 0xA0000000
93 #define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
94 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
95 #define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
96 #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
97 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
102 #define CONFIG_MXC_UART
103 #define CONFIG_SYS_MX27_UART1
104 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
105 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
106 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
109 * Flash & Environment
111 #define CONFIG_ENV_IS_IN_FLASH
112 #define CONFIG_FLASH_CFI_DRIVER
113 #define CONFIG_SYS_FLASH_CFI
114 /* Use buffered writes (~10x faster) */
115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
116 /* Use hardware sector protection */
117 #define CONFIG_SYS_FLASH_PROTECTION 1
118 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
119 /* CS2 Base address */
120 #define PHYS_FLASH_1 0xc0000000
121 /* Flash Base for U-Boot */
122 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
123 #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \
124 CONFIG_SYS_FLASH_SECT_SZ)
125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
126 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
127 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
128 /* Address and size of Redundant Environment Sector */
129 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
130 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
135 #define CONFIG_FEC_MXC
136 #define CONFIG_FEC_MXC_PHYADDR 0x1f
138 #define CONFIG_NET_MULTI
143 #define CONFIG_FLASH_CFI_MTD
144 #define CONFIG_MTD_DEVICE
149 #define CONFIG_NAND_MXC
150 #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
151 #define CONFIG_SYS_MAX_NAND_DEVICE 1
152 #define CONFIG_SYS_NAND_BASE 0xd8000000
153 #define CONFIG_JFFS2_NAND
154 #define CONFIG_MXC_NAND_HWECC
155 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
161 #define CONFIG_GENERIC_MMC
162 #define CONFIG_MXC_MMC
163 #define CONFIG_DOS_PARTITION
168 #define CONFIG_CMD_MTDPARTS
171 * U-Boot general configuration
173 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
174 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
175 /* Print buffer sz */
176 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
177 sizeof(CONFIG_SYS_PROMPT) + 16)
178 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
179 /* Boot Argument Buffer Size */
180 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
181 #define CONFIG_CMDLINE_EDITING
182 #define CONFIG_SYS_LONGHELP
187 #include <config_cmd_default.h>
188 #define CONFIG_CMD_ASKENV
189 #define CONFIG_CMD_CACHE
190 #define CONFIG_CMD_DHCP
191 #define CONFIG_CMD_DIAG
192 #define CONFIG_CMD_FAT
193 #define CONFIG_CMD_JFFS2
194 #define CONFIG_CMD_MII
195 #define CONFIG_CMD_MMC
196 #define CONFIG_CMD_NAND
197 #define CONFIG_CMD_PING
199 #define CONFIG_BOOTDELAY 5
201 #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
202 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
204 #define xstr(s) str(s)
207 #define CONFIG_EXTRA_ENV_SETTINGS \
209 "nfsargs=setenv bootargs root=/dev/nfs rw " \
210 "nfsroot=${serverip}:${rootpath}\0" \
211 "ramargs=setenv bootargs root=/dev/ram rw\0" \
212 "addip=setenv bootargs ${bootargs} " \
213 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
214 ":${hostname}:${netdev}:off panic=1\0" \
215 "addtty=setenv bootargs ${bootargs}" \
216 " console=ttymxc0,${baudrate}\0" \
217 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
218 "addmisc=setenv bootargs ${bootargs}\0" \
219 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
220 "kernel_addr_r=a0800000\0" \
221 "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
222 "rootpath=/opt/eldk-4.2-arm/arm\0" \
223 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
224 "run nfsargs addip addtty addmtd addmisc;" \
226 "bootcmd=run net_nfs\0" \
227 "load=tftp ${loadaddr} ${u-boot}\0" \
228 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
229 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
230 " +${filesize};cp.b ${fileaddr} " \
231 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
232 "upd=run load update\0" \
233 "mtdids=" MTDIDS_DEFAULT "\0" \
234 "mtdparts=" MTDPARTS_DEFAULT "\0" \
236 /* additions for new relocation code, must be added to all boards */
237 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
238 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
239 GENERATED_GBL_DATA_SIZE)
240 #endif /* __IMX27LITE_COMMON_CONFIG_H */