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[u-boot] / include / configs / imx27lite-common.h
1 /*
2  * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
3  *
4  * based on:
5  * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __IMX27LITE_COMMON_CONFIG_H
11 #define __IMX27LITE_COMMON_CONFIG_H
12
13 /*
14  * SoC Configuration
15  */
16 #define CONFIG_MX27
17 #define CONFIG_MX27_CLK32       32768           /* OSC32K frequency */
18
19 #define CONFIG_SYS_TEXT_BASE            0xc0000000
20
21 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
22 #define CONFIG_SETUP_MEMORY_TAGS        1
23 #define CONFIG_INITRD_TAG               1
24
25 /*
26  * Lowlevel configuration
27  */
28 #define SDRAM_ESDCFG_REGISTER_VAL(cas)  \
29                 (ESDCFG_TRC(10) |       \
30                 ESDCFG_TRCD(3) |        \
31                 ESDCFG_TCAS(cas) |      \
32                 ESDCFG_TRRD(1) |        \
33                 ESDCFG_TRAS(5) |        \
34                 ESDCFG_TWR |            \
35                 ESDCFG_TMRD(2) |        \
36                 ESDCFG_TRP(2) |         \
37                 ESDCFG_TXP(3))
38
39 #define SDRAM_ESDCTL_REGISTER_VAL       \
40                 (ESDCTL_PRCT(0) |       \
41                  ESDCTL_BL |            \
42                  ESDCTL_PWDT(0) |       \
43                  ESDCTL_SREFR(3) |      \
44                  ESDCTL_DSIZ_32 |       \
45                  ESDCTL_COL10 |         \
46                  ESDCTL_ROW13 |         \
47                  ESDCTL_SDE)
48
49 #define SDRAM_ALL_VAL           0xf00
50
51 #define SDRAM_MODE_REGISTER_VAL 0x33    /* BL: 8, CAS: 3 */
52 #define SDRAM_EXT_MODE_REGISTER_VAL     0x1000000
53
54 #define MPCTL0_VAL      0x1ef15d5
55
56 #define SPCTL0_VAL      0x043a1c09
57
58 #define CSCR_VAL        0x33f08107
59
60 #define PCDR0_VAL       0x120470c3
61 #define PCDR1_VAL       0x03030303
62 #define PCCR0_VAL       0xffffffff
63 #define PCCR1_VAL       0xfffffffc
64
65 #define AIPI1_PSR0_VAL  0x20040304
66 #define AIPI1_PSR1_VAL  0xdffbfcfb
67 #define AIPI2_PSR0_VAL  0x07ffc200
68 #define AIPI2_PSR1_VAL  0xffffffff
69
70 /*
71  * Memory Info
72  */
73 /* malloc() len */
74 #define CONFIG_SYS_MALLOC_LEN           (0x10000 + 512 * 1024)
75 /* memtest start address */
76 #define CONFIG_SYS_MEMTEST_START        0xA0000000
77 #define CONFIG_SYS_MEMTEST_END          0xA1000000      /* 16MB RAM test */
78 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
79 #define PHYS_SDRAM_1            0xA0000000      /* DDR Start */
80 #define PHYS_SDRAM_1_SIZE       0x08000000      /* DDR size 128MB */
81
82 /*
83  * Serial Driver info
84  */
85 #define CONFIG_MXC_UART
86 #define CONFIG_MXC_UART_BASE    UART1_BASE
87 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
88 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
89
90 /*
91  * Flash & Environment
92  */
93 #define CONFIG_ENV_IS_IN_FLASH
94 #define CONFIG_FLASH_CFI_DRIVER
95 #define CONFIG_SYS_FLASH_CFI
96 /* Use buffered writes (~10x faster) */
97 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
98 /* Use hardware sector protection */
99 #define CONFIG_SYS_FLASH_PROTECTION             1
100 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of flash banks */
101 /* CS2 Base address */
102 #define PHYS_FLASH_1                    0xc0000000
103 /* Flash Base for U-Boot */
104 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
105 #define CONFIG_SYS_MAX_FLASH_SECT       (PHYS_FLASH_SIZE / \
106                 CONFIG_SYS_FLASH_SECT_SZ)
107 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
108 #define CONFIG_SYS_MONITOR_LEN          0x40000         /* Reserve 256KiB */
109 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
110 /* Address and size of Redundant Environment Sector     */
111 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
112 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
113
114 /*
115  * Ethernet
116  */
117 #define CONFIG_FEC_MXC
118 #define CONFIG_FEC_MXC_PHYADDR          0x1f
119 #define CONFIG_MII
120
121 /*
122  * MTD
123  */
124 #define CONFIG_FLASH_CFI_MTD
125 #define CONFIG_MTD_DEVICE
126
127 /*
128  * NAND
129  */
130 #define CONFIG_NAND_MXC
131 #define CONFIG_MXC_NAND_REGS_BASE       0xd8000000
132 #define CONFIG_SYS_MAX_NAND_DEVICE      1
133 #define CONFIG_SYS_NAND_BASE            0xd8000000
134 #define CONFIG_JFFS2_NAND
135 #define CONFIG_MXC_NAND_HWECC
136
137 /*
138  * SD/MMC
139  */
140 #define CONFIG_MMC
141 #define CONFIG_GENERIC_MMC
142 #define CONFIG_MXC_MMC
143 #define CONFIG_DOS_PARTITION
144
145 /*
146  * GPIO
147  */
148 #define CONFIG_MXC_GPIO
149
150 /*
151  * MTD partitions
152  */
153 #define CONFIG_CMD_MTDPARTS
154
155 /*
156  * U-Boot general configuration
157  */
158 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size  */
159 /* Print buffer sz */
160 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
161                 sizeof(CONFIG_SYS_PROMPT) + 16)
162 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
163 /* Boot Argument Buffer Size */
164 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
165 #define CONFIG_CMDLINE_EDITING
166 #define CONFIG_SYS_LONGHELP
167
168 /*
169  * U-Boot commands
170  */
171 #define CONFIG_CMD_DIAG
172 #define CONFIG_CMD_JFFS2
173 #define CONFIG_CMD_NAND
174
175
176 #define CONFIG_LOADADDR         0xa0800000      /* loadaddr env var */
177 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
178
179 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
180         "netdev=eth0\0"                                                 \
181         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
182                 "nfsroot=${serverip}:${rootpath}\0"                     \
183         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
184         "addip=setenv bootargs ${bootargs} "                            \
185                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
186                 ":${hostname}:${netdev}:off panic=1\0"                  \
187         "addtty=setenv bootargs ${bootargs}"                            \
188                 " console=ttymxc0,${baudrate}\0"                        \
189         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
190         "addmisc=setenv bootargs ${bootargs}\0"                         \
191         "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"          \
192         "kernel_addr_r=a0800000\0"                                      \
193         "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"            \
194         "rootpath=/opt/eldk-4.2-arm/arm\0"                              \
195         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
196                 "run nfsargs addip addtty addmtd addmisc;"              \
197                 "bootm\0"                                               \
198         "bootcmd=run net_nfs\0"                                         \
199         "load=tftp ${loadaddr} ${u-boot}\0"                             \
200         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
201                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
202                 " +${filesize};cp.b ${fileaddr} "                       \
203                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
204         "upd=run load update\0"                                         \
205         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
206         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
207
208 /* additions for new relocation code, must be added to all boards */
209 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
210 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
211                                         GENERATED_GBL_DATA_SIZE)
212 #endif /* __IMX27LITE_COMMON_CONFIG_H */