4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
7 * Configuration settings for the LogicPD i.MX31 Litekit board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/imx-regs.h>
33 /* High Level Configuration Options */
34 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35 #define CONFIG_MX31 1 /* in a mx31 */
36 #define CONFIG_MX31_HCLK_FREQ 26000000
37 #define CONFIG_MX31_CLK32 32000
39 #define CONFIG_DISPLAY_CPUINFO
40 #define CONFIG_DISPLAY_BOARDINFO
42 #define CONFIG_SYS_TEXT_BASE 0xa0000000
44 #define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
46 /* Temporarily disabled */
48 #define CONFIG_OF_LIBFDT 1
50 #define CONFIG_FIT_VERBOSE 1
53 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
54 #define CONFIG_SETUP_MEMORY_TAGS 1
55 #define CONFIG_INITRD_TAG 1
58 * Size of malloc() pool
60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
66 #define CONFIG_MXC_UART 1
67 #define CONFIG_SYS_MX31_UART1 1
68 #define CONFIG_MXC_GPIO
70 #define CONFIG_HARD_SPI 1
71 #define CONFIG_MXC_SPI 1
72 #define CONFIG_DEFAULT_SPI_BUS 1
73 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
75 #define CONFIG_FSL_PMIC
76 #define CONFIG_FSL_PMIC_BUS 1
77 #define CONFIG_FSL_PMIC_CS 0
78 #define CONFIG_FSL_PMIC_CLK 1000000
79 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
81 #define CONFIG_RTC_MC13783 1
83 /* allow to overwrite serial and ethaddr */
84 #define CONFIG_ENV_OVERWRITE
85 #define CONFIG_CONS_INDEX 1
86 #define CONFIG_BAUDRATE 115200
87 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
89 /***********************************************************
91 ***********************************************************/
93 #include <config_cmd_default.h>
95 #define CONFIG_CMD_MII
96 #define CONFIG_CMD_PING
97 #define CONFIG_CMD_SPI
98 #define CONFIG_CMD_DATE
99 #define CONFIG_CMD_NAND
101 #define CONFIG_BOOTDELAY 3
103 #define CONFIG_NETMASK 255.255.255.0
104 #define CONFIG_IPADDR 192.168.23.168
105 #define CONFIG_SERVERIP 192.168.23.2
107 #define CONFIG_EXTRA_ENV_SETTINGS \
108 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
109 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
110 "bootcmd=run bootcmd_net\0" \
111 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
112 "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
115 #define CONFIG_SMC911X 1
116 #define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
117 #define CONFIG_SMC911X_32_BIT 1
120 * Miscellaneous configurable options
122 #define CONFIG_SYS_LONGHELP /* undef to save memory */
123 #define CONFIG_SYS_PROMPT "uboot> "
124 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
125 /* Print Buffer Size */
126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
127 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
130 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
131 #define CONFIG_SYS_MEMTEST_END 0x10000
133 #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
135 #define CONFIG_SYS_HZ 1000
137 #define CONFIG_CMDLINE_EDITING 1
139 /*-----------------------------------------------------------------------
142 * The stack sizes are set up in start.S using the settings below
144 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
146 /*-----------------------------------------------------------------------
147 * Physical Memory Map
149 #define CONFIG_NR_DRAM_BANKS 1
150 #define PHYS_SDRAM_1 CSD0_BASE
151 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
152 #define CONFIG_BOARD_EARLY_INIT_F
154 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
155 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
156 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
157 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
158 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
160 /*-----------------------------------------------------------------------
161 * FLASH and environment organization
163 #define CONFIG_SYS_FLASH_BASE CS0_BASE
164 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
165 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
168 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
169 #define CONFIG_ENV_IS_IN_FLASH 1
170 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
171 #define CONFIG_ENV_SIZE (64 * 1024)
173 /*-----------------------------------------------------------------------
174 * CFI FLASH driver setup
176 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
177 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
179 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
181 /* timeout values are in ticks */
182 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
183 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
188 #undef CONFIG_CMD_MTDPARTS
189 #define CONFIG_JFFS2_DEV "nor0"
194 #define CONFIG_NAND_MXC
195 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
196 #define CONFIG_SYS_MAX_NAND_DEVICE 1
197 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
198 #define CONFIG_MXC_NAND_HWECC
200 #endif /* __CONFIG_H */