4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
7 * Configuration settings for the phyCORE-i.MX31 board.
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/imx-regs.h>
17 /* High Level Configuration Options */
18 #define CONFIG_MX31 /* This is a mx31 */
19 #define CONFIG_MX31_CLK32 32000
21 #define CONFIG_DISPLAY_CPUINFO
22 #define CONFIG_DISPLAY_BOARDINFO
24 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
25 #define CONFIG_SETUP_MEMORY_TAGS
26 #define CONFIG_INITRD_TAG
29 * Size of malloc() pool
31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
37 #define CONFIG_SYS_I2C
38 #define CONFIG_SYS_I2C_MXC
39 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
40 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
41 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
42 #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
44 #define CONFIG_MXC_UART
45 #define CONFIG_MXC_UART_BASE UART1_BASE
47 /* allow to overwrite serial and ethaddr */
48 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_CONS_INDEX 1
50 #define CONFIG_BAUDRATE 115200
52 /***********************************************************
54 ***********************************************************/
55 #define CONFIG_CMD_EEPROM
58 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
59 "1536k(kernel),-(root)"
61 #define CONFIG_NETMASK 255.255.255.0
62 #define CONFIG_IPADDR 192.168.23.168
63 #define CONFIG_SERVERIP 192.168.23.2
65 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
67 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
68 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
69 "bootargs_flash=setenv bootargs $(bootargs) " \
70 "root=/dev/mtdblock2 rootfstype=jffs2\0" \
71 "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
72 "bootcmd=run bootcmd_net\0" \
73 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
74 "tftpboot 0x80000000 $(uimage);bootm\0" \
75 "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
76 "bootm 0x80000000\0" \
78 "mtdparts=" MTDPARTS_DEFAULT "\0" \
79 "prg_uboot=tftpboot 0x80000000 $(uboot);" \
80 "protect off 0xa0000000 +0x20000;" \
81 "erase 0xa0000000 +0x20000;" \
82 "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
83 "prg_kernel=tftpboot 0x80000000 $(uimage);" \
84 "erase 0xa0040000 +0x180000;" \
85 "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
86 "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
87 "erase 0xa01c0000 0xa1ffffff;" \
88 "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
89 "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
90 "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
91 "sync:1241513985,vmode:0\0"
93 #define CONFIG_SMC911X
94 #define CONFIG_SMC911X_BASE 0xa8000000
95 #define CONFIG_SMC911X_32_BIT
98 * Miscellaneous configurable options
100 #define CONFIG_SYS_LONGHELP /* undef to save memory */
101 /* Console I/O Buffer Size */
102 #define CONFIG_SYS_CBSIZE 256
103 /* Print Buffer Size */
104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
105 sizeof(CONFIG_SYS_PROMPT) + 16)
106 /* max number of command args */
107 #define CONFIG_SYS_MAXARGS 16
108 /* Boot Argument Buffer Size */
109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
111 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
112 #define CONFIG_SYS_MEMTEST_END 0x10000
114 #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
116 #define CONFIG_CMDLINE_EDITING
119 * Physical Memory Map
121 #define CONFIG_NR_DRAM_BANKS 1
122 #define PHYS_SDRAM_1 0x80000000
123 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
124 #define CONFIG_BOARD_EARLY_INIT_F
125 #define CONFIG_SYS_TEXT_BASE 0xA0000000
127 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
128 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
129 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
130 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
131 GENERATED_GBL_DATA_SIZE)
132 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
133 CONFIG_SYS_GBL_DATA_OFFSET)
136 * FLASH and environment organization
138 #define CONFIG_SYS_FLASH_BASE 0xa0000000
139 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
140 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
141 /* Monitor at beginning of flash */
142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
144 #define CONFIG_ENV_IS_IN_EEPROM
145 #define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
146 #define CONFIG_ENV_SIZE 4096
147 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
149 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
153 * CFI FLASH driver setup
155 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
156 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
158 #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
161 * Timeout for Flash Erase and Flash Write
162 * timeout values are in ticks
164 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
165 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
170 #undef CONFIG_CMD_MTDPARTS
171 #define CONFIG_JFFS2_DEV "nor0"
173 /* EET platform additions */
174 #ifdef CONFIG_IMX31_PHYCORE_EET
175 #define CONFIG_BOARD_LATE_INIT
177 #define CONFIG_MXC_GPIO
179 #define CONFIG_HARD_SPI
180 #define CONFIG_MXC_SPI
182 #define CONFIG_S6E63D6
185 #define CONFIG_CFB_CONSOLE
186 #define CONFIG_VIDEO_MX3
187 #define CONFIG_VIDEO_LOGO
188 #define CONFIG_VIDEO_SW_CURSOR
189 #define CONFIG_VGA_AS_SINGLE_DEVICE
190 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
191 #define CONFIG_SPLASH_SCREEN
192 #define CONFIG_CMD_BMP
193 #define CONFIG_BMP_16BPP
196 #endif /* __CONFIG_H */