3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
5 * (C) Copyright 2003-2005
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
15 * High Level Configuration Options
19 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
20 #define CONFIG_INKA4X0 1 /* INKA4x0 board */
21 #define CONFIG_DISPLAY_BOARDINFO
24 * Valid values for CONFIG_SYS_TEXT_BASE are:
26 * 0x00100000 boot from RAM (for testing only)
28 #ifndef CONFIG_SYS_TEXT_BASE
29 #define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */
31 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
33 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
35 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
37 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
40 * Serial console configuration
42 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
43 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
48 * 0x40000000 - 0x4fffffff - PCI Memory
49 * 0x50000000 - 0x50ffffff - PCI IO Space
52 #define CONFIG_PCI_PNP 1
53 #define CONFIG_PCI_SCAN_SHOW 1
54 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
56 #define CONFIG_PCI_MEM_BUS 0x40000000
57 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
58 #define CONFIG_PCI_MEM_SIZE 0x10000000
60 #define CONFIG_PCI_IO_BUS 0x50000000
61 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
62 #define CONFIG_PCI_IO_SIZE 0x01000000
64 #define CONFIG_SYS_XLB_PIPELINING 1
67 #define CONFIG_MAC_PARTITION
68 #define CONFIG_DOS_PARTITION
69 #define CONFIG_ISO_PARTITION
75 #define CONFIG_BOOTP_BOOTFILESIZE
76 #define CONFIG_BOOTP_BOOTPATH
77 #define CONFIG_BOOTP_GATEWAY
78 #define CONFIG_BOOTP_HOSTNAME
82 * Command line configuration.
84 #define CONFIG_CMD_DATE
85 #define CONFIG_CMD_EXT2
86 #define CONFIG_CMD_FAT
87 #define CONFIG_CMD_IDE
88 #define CONFIG_CMD_PCI
90 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
92 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */
93 # define CONFIG_SYS_LOWBOOT 1
99 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
101 #define CONFIG_PREBOOT "echo;" \
102 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
105 #undef CONFIG_BOOTARGS
107 #define CONFIG_IPADDR 192.168.100.2
108 #define CONFIG_SERVERIP 192.168.100.1
109 #define CONFIG_NETMASK 255.255.255.0
110 #define HOSTNAME inka4x0
111 #define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage"
112 #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
114 #define CONFIG_EXTRA_ENV_SETTINGS \
116 "nfsargs=setenv bootargs root=/dev/nfs rw " \
117 "nfsroot=${serverip}:${rootpath}\0" \
118 "ramargs=setenv bootargs root=/dev/ram rw\0" \
119 "addip=setenv bootargs ${bootargs} " \
120 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
121 ":${hostname}:${netdev}:off panic=1\0" \
122 "addcons=setenv bootargs ${bootargs} " \
123 "console=ttyS0,${baudrate}\0" \
124 "flash_nfs=run nfsargs addip addcons;" \
125 "bootm ${kernel_addr}\0" \
126 "net_nfs=tftp 200000 ${bootfile};" \
127 "run nfsargs addip addcons;bootm\0" \
128 "enable_disp=mw.l 100000 04000000 1;" \
129 "cp.l 100000 f0000b20 1;" \
130 "cp.l 100000 f0000b28 1\0" \
131 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
132 "ide_boot=ext2load ide 0:1 200000 uImage;" \
133 "run ideargs addip addcons enable_disp;bootm\0" \
137 #define CONFIG_BOOTCOMMAND "run ide_boot"
140 * IPB Bus clocking configuration.
142 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
145 * Flash configuration
147 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
148 #define CONFIG_FLASH_CFI_DRIVER 1
149 #define CONFIG_SYS_FLASH_BASE 0xffe00000
150 #define CONFIG_SYS_FLASH_SIZE 0x00200000
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
152 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
153 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
157 * Environment settings
159 #define CONFIG_ENV_IS_IN_FLASH 1
160 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
161 #define CONFIG_ENV_SIZE 0x2000
162 #define CONFIG_ENV_SECT_SIZE 0x2000
163 #define CONFIG_ENV_OVERWRITE 1
164 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
169 #define CONFIG_SYS_MBAR 0xF0000000
170 #define CONFIG_SYS_SDRAM_BASE 0x00000000
171 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
174 * SDRAM controller configuration
176 #undef CONFIG_SDR_MT48LC16M16A2
177 #undef CONFIG_DDR_MT46V16M16
178 #undef CONFIG_DDR_MT46V32M16
179 #undef CONFIG_DDR_HYB25D512160BF
180 #define CONFIG_DDR_K4H511638C
182 /* Use ON-Chip SRAM until RAM will be available */
183 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
185 /* preserve space for the post_word at end of on-chip SRAM */
186 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
189 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
191 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
194 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
195 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
197 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
198 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
199 # define CONFIG_SYS_RAMBOOT 1
202 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
203 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
204 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
207 * Ethernet configuration
209 #define CONFIG_MPC5xxx_FEC 1
210 #define CONFIG_MPC5xxx_FEC_MII100
212 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
214 /* #define CONFIG_MPC5xxx_FEC_MII10 */
215 #define CONFIG_PHY_ADDR 0x00
221 * use CS1 as gpio_wkup_6 output
222 * Bit 0 (mask: 0x80000000): 0
223 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
224 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
225 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
227 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
228 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
229 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
230 * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
232 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
237 #define CONFIG_RTC_RTC4543 1 /* use external RTC */
240 * Software (bit-bang) three wire serial configuration
242 * Note that we need the ifdefs because otherwise compilation of
245 #define CONFIG_SOFT_TWS 1
247 #ifdef TWS_IMPLEMENTATION
251 #define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
252 #define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
253 #define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
254 #define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
256 static inline void tws_ce(unsigned bit)
258 struct mpc5xxx_wu_gpio *wu_gpio =
259 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
261 setbits_8(&wu_gpio->dvo, TWS_CE);
263 clrbits_8(&wu_gpio->dvo, TWS_CE);
266 static inline void tws_wr(unsigned bit)
268 struct mpc5xxx_wu_gpio *wu_gpio =
269 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
271 setbits_8(&wu_gpio->dvo, TWS_WR);
273 clrbits_8(&wu_gpio->dvo, TWS_WR);
276 static inline void tws_clk(unsigned bit)
278 struct mpc5xxx_gpio *gpio =
279 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
281 setbits_8(&gpio->sint_dvo, TWS_CLK);
283 clrbits_8(&gpio->sint_dvo, TWS_CLK);
286 static inline void tws_data(unsigned bit)
288 struct mpc5xxx_gpio *gpio =
289 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
291 setbits_8(&gpio->sint_dvo, TWS_DATA);
293 clrbits_8(&gpio->sint_dvo, TWS_DATA);
296 static inline unsigned tws_data_read(void)
298 struct mpc5xxx_gpio *gpio =
299 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
300 return !!(in_8(&gpio->sint_ival) & TWS_DATA);
303 static inline void tws_data_config_output(unsigned output)
305 struct mpc5xxx_gpio *gpio =
306 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
308 setbits_8(&gpio->sint_ddr, TWS_DATA);
310 clrbits_8(&gpio->sint_ddr, TWS_DATA);
312 #endif /* TWS_IMPLEMENTATION */
315 * Miscellaneous configurable options
317 #define CONFIG_SYS_LONGHELP /* undef to save memory */
318 #if defined(CONFIG_CMD_KGDB)
319 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
321 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
323 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
324 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
325 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
327 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
328 #if defined(CONFIG_CMD_KGDB)
329 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
332 /* Enable an alternate, more extensive memory test */
333 #define CONFIG_SYS_ALT_MEMTEST
335 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
336 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
338 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
341 * Various low-level settings
343 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
344 #define CONFIG_SYS_HID0_FINAL HID0_ICE
346 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
347 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
348 #define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
349 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
350 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
352 /* 32Mbit SRAM @0x30000000 */
353 #define CONFIG_SYS_CS1_START 0x30000000
354 #define CONFIG_SYS_CS1_SIZE 0x00400000
355 #define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
357 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
358 #define CONFIG_SYS_CS2_START 0x80000000
359 #define CONFIG_SYS_CS2_SIZE 0x0001000
360 #define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
362 /* GPIO in @0x30400000 */
363 #define CONFIG_SYS_CS3_START 0x30400000
364 #define CONFIG_SYS_CS3_SIZE 0x00100000
365 #define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
367 #define CONFIG_SYS_CS_BURST 0x00000000
368 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
370 /*-----------------------------------------------------------------------
372 *-----------------------------------------------------------------------
374 #define CONFIG_USB_OHCI
375 #define CONFIG_USB_CLOCK 0x00015555
376 #define CONFIG_USB_CONFIG 0x00001000
377 #define CONFIG_USB_STORAGE
379 /*-----------------------------------------------------------------------
380 * IDE/ATA stuff Supports IDE harddisk
381 *-----------------------------------------------------------------------
384 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
386 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
387 #undef CONFIG_IDE_LED /* LED for ide not supported */
389 #define CONFIG_IDE_PREINIT
391 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
392 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
394 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
395 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
396 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
397 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
398 #define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
399 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
401 #define CONFIG_ATAPI 1
403 #define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
405 #endif /* __CONFIG_H */