4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Integrator AP board.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #define CONFIG_INTEGRATOR
35 #define CONFIG_ARCH_INTEGRATOR
37 * High Level Configuration Options
40 #define CONFIG_SYS_MEMTEST_START 0x100000
41 #define CONFIG_SYS_MEMTEST_END 0x10000000
42 #define CONFIG_SYS_HZ 1000
43 #define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
44 #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
46 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
47 #define CONFIG_SETUP_MEMORY_TAGS 1
48 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
50 #define CONFIG_SKIP_LOWLEVEL_INIT
51 #define CONFIG_CM_INIT 1
52 #define CONFIG_CM_REMAP 1
53 #define CONFIG_CM_SPD_DETECT
56 * Size of malloc() pool
58 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
63 #define CONFIG_PL010_SERIAL
64 #define CONFIG_CONS_INDEX 0
65 #define CONFIG_BAUDRATE 38400
66 #define CONFIG_PL01x_PORTS { (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) }
67 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
68 #define CONFIG_SYS_SERIAL0 0x16000000
69 #define CONFIG_SYS_SERIAL1 0x17000000
75 #define CONFIG_BOOTP_BOOTFILESIZE
76 #define CONFIG_BOOTP_BOOTPATH
77 #define CONFIG_BOOTP_GATEWAY
78 #define CONFIG_BOOTP_HOSTNAME
82 * Command line configuration.
86 #define CONFIG_CMD_IMI
87 #define CONFIG_CMD_BDI
88 #define CONFIG_CMD_BOOTD
89 #define CONFIG_CMD_MEMORY
90 #define CONFIG_CMD_FLASH
91 #define CONFIG_CMD_IMLS
92 #define CONFIG_CMD_LOADB
93 #define CONFIG_CMD_LOADS
96 #define CONFIG_BOOTDELAY 2
97 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty"
98 #define CONFIG_BOOTCOMMAND ""
101 * Miscellaneous configurable options
103 #define CONFIG_SYS_LONGHELP /* undef to save memory */
104 #define CONFIG_SYS_HUSH_PARSER
105 #define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
106 #define CONFIG_SYS_PROMPT_HUSH_PS2 "# "
107 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
108 /* Print Buffer Size */
109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113 #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
115 /*-----------------------------------------------------------------------
118 * The stack sizes are set up in start.S using the settings below
120 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
121 #ifdef CONFIG_USE_IRQ
122 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
123 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
126 /*-----------------------------------------------------------------------
127 * Physical Memory Map
129 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
130 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
131 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
132 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
133 #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
134 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
135 CONFIG_SYS_INIT_RAM_SIZE - \
136 GENERATED_GBL_DATA_SIZE)
137 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
139 #define CONFIG_SYS_FLASH_BASE 0x24000000
141 /*-----------------------------------------------------------------------
142 * FLASH and environment organization
144 #define CONFIG_SYS_FLASH_CFI 1
145 #define CONFIG_FLASH_CFI_DRIVER 1
146 #define CONFIG_ENV_IS_NOWHERE
147 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
148 /* timeout values are in ticks */
149 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
150 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
151 #define CONFIG_SYS_MAX_FLASH_SECT 128
152 #define CONFIG_ENV_SIZE 32768
155 /*-----------------------------------------------------------------------
159 #ifdef CONFIG_PCI /* pci support */
160 #undef CONFIG_PCI_PNP
161 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
164 #define CONFIG_EEPRO100
165 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
167 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
168 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
171 #define INTEGRATOR_PCI_BASE 0x40000000
172 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
174 /* memory map as seen by the CPU on the local bus */
175 #define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
176 #define CPU_PCI_IO_SIZE 0x10000
178 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
179 #define CPU_PCI_CNFG_SIZE 0x1000000
181 #define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
182 /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
183 #define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
184 /* unused (128-16)M from B1000000-B7FFFFFF */
185 #define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
186 /* unused ((128-16)M - 64K) from XXX */
188 #define PCI_V3_BASE 0x62000000
190 /* V3 PCI bridge controller */
191 #define V3_BASE 0x62000000 /* V360EPC registers */
193 #define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS)
194 #define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
197 #define V3_PCI_VENDOR 0x00000000
198 #define V3_PCI_DEVICE 0x00000002
199 #define V3_PCI_CMD 0x00000004
200 #define V3_PCI_STAT 0x00000006
201 #define V3_PCI_CC_REV 0x00000008
202 #define V3_PCI_HDR_CF 0x0000000C
203 #define V3_PCI_IO_BASE 0x00000010
204 #define V3_PCI_BASE0 0x00000014
205 #define V3_PCI_BASE1 0x00000018
206 #define V3_PCI_SUB_VENDOR 0x0000002C
207 #define V3_PCI_SUB_ID 0x0000002E
208 #define V3_PCI_ROM 0x00000030
209 #define V3_PCI_BPARAM 0x0000003C
210 #define V3_PCI_MAP0 0x00000040
211 #define V3_PCI_MAP1 0x00000044
212 #define V3_PCI_INT_STAT 0x00000048
213 #define V3_PCI_INT_CFG 0x0000004C
214 #define V3_LB_BASE0 0x00000054
215 #define V3_LB_BASE1 0x00000058
216 #define V3_LB_MAP0 0x0000005E
217 #define V3_LB_MAP1 0x00000062
218 #define V3_LB_BASE2 0x00000064
219 #define V3_LB_MAP2 0x00000066
220 #define V3_LB_SIZE 0x00000068
221 #define V3_LB_IO_BASE 0x0000006E
222 #define V3_FIFO_CFG 0x00000070
223 #define V3_FIFO_PRIORITY 0x00000072
224 #define V3_FIFO_STAT 0x00000074
225 #define V3_LB_ISTAT 0x00000076
226 #define V3_LB_IMASK 0x00000077
227 #define V3_SYSTEM 0x00000078
228 #define V3_LB_CFG 0x0000007A
229 #define V3_PCI_CFG 0x0000007C
230 #define V3_DMA_PCI_ADR0 0x00000080
231 #define V3_DMA_PCI_ADR1 0x00000090
232 #define V3_DMA_LOCAL_ADR0 0x00000084
233 #define V3_DMA_LOCAL_ADR1 0x00000094
234 #define V3_DMA_LENGTH0 0x00000088
235 #define V3_DMA_LENGTH1 0x00000098
236 #define V3_DMA_CSR0 0x0000008B
237 #define V3_DMA_CSR1 0x0000009B
238 #define V3_DMA_CTLB_ADR0 0x0000008C
239 #define V3_DMA_CTLB_ADR1 0x0000009C
240 #define V3_DMA_DELAY 0x000000E0
241 #define V3_MAIL_DATA 0x000000C0
242 #define V3_PCI_MAIL_IEWR 0x000000D0
243 #define V3_PCI_MAIL_IERD 0x000000D2
244 #define V3_LB_MAIL_IEWR 0x000000D4
245 #define V3_LB_MAIL_IERD 0x000000D6
246 #define V3_MAIL_WR_STAT 0x000000D8
247 #define V3_MAIL_RD_STAT 0x000000DA
248 #define V3_QBA_MAP 0x000000DC
250 /* SYSTEM register bits */
251 #define V3_SYSTEM_M_RST_OUT (1 << 15)
252 #define V3_SYSTEM_M_LOCK (1 << 14)
255 #define V3_PCI_CFG_M_RETRY_EN (1 << 10)
256 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
257 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
259 /* PCI MAP register bits (PCI -> Local bus) */
260 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
261 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
262 #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
263 #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
264 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
265 #define V3_PCI_MAP_M_REG_EN (1 << 1)
266 #define V3_PCI_MAP_M_ENABLE (1 << 0)
268 /* 9 => 512M window size */
269 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
271 /* A => 1024M window size */
272 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
274 /* LB_BASE register bits (Local bus -> PCI) */
275 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000
276 #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
277 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0
278 #define V3_LB_BASE_M_PREFETCH (1 << 3)
279 #define V3_LB_BASE_M_ENABLE (1 << 0)
281 /* PCI COMMAND REGISTER bits */
282 #define V3_COMMAND_M_FBB_EN (1 << 9)
283 #define V3_COMMAND_M_SERR_EN (1 << 8)
284 #define V3_COMMAND_M_PAR_EN (1 << 6)
285 #define V3_COMMAND_M_MASTER_EN (1 << 2)
286 #define V3_COMMAND_M_MEM_EN (1 << 1)
287 #define V3_COMMAND_M_IO_EN (1 << 0)
289 #define INTEGRATOR_SC_BASE 0x11000000
290 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
291 #define INTEGRATOR_SC_PCIENABLE \
292 (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
294 #endif /* CONFIG_PCI */
295 /*-----------------------------------------------------------------------
296 * There are various dependencies on the core module (CM) fitted
297 * Users should refer to their CM user guide
298 * - when porting adjust u-boot/Makefile accordingly
299 * to define the necessary CONFIG_ s for the CM involved
300 * see e.g. integratorcp_CM926EJ-S_config
302 #include "armcoremodule.h"
304 #endif /* __CONFIG_H */