4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Integrator AP board.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * High Level Configuration Options
38 #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39 #define CONFIG_INTEGRATOR 1 /* in an Integrator board */
40 #define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */
43 #define CFG_MEMTEST_START 0x100000
44 #define CFG_MEMTEST_END 0x10000000
45 #define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */
46 #define CFG_TIMERBASE 0x13000100
48 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
49 #define CONFIG_SETUP_MEMORY_TAGS 1
50 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
52 * Size of malloc() pool
54 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
59 #define CFG_PL010_SERIAL
60 #define CONFIG_CONS_INDEX 0
61 #define CONFIG_BAUDRATE 38400
62 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
63 #define CFG_SERIAL0 0x16000000
64 #define CFG_SERIAL1 0x17000000
66 //#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI)
67 //#define CONFIG_NET_MULTI
68 //#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
70 #define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
73 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
74 #include <cmd_confdefs.h>
76 #define CONFIG_BOOTDELAY 2
77 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
78 #define CONFIG_BOOTCOMMAND ""
81 * Miscellaneous configurable options
83 #define CFG_LONGHELP /* undef to save memory */
84 #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
85 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
86 /* Print Buffer Size */
87 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
88 #define CFG_MAXARGS 16 /* max number of command args */
89 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
91 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
92 #define CFG_LOAD_ADDR 0x7fc0 /* default load address */
94 /*-----------------------------------------------------------------------
97 * The stack sizes are set up in start.S using the settings below
99 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
100 #ifdef CONFIG_USE_IRQ
101 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
102 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
105 /*-----------------------------------------------------------------------
106 * Physical Memory Map
108 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
109 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
110 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
112 #define CFG_FLASH_BASE 0x24000000
114 /*-----------------------------------------------------------------------
115 * FLASH and environment organization
117 #define CFG_ENV_IS_NOWHERE
118 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
119 #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
120 /* timeout values are in ticks */
121 #define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
122 #define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
123 #define CFG_MAX_FLASH_SECT 128
124 #define CFG_ENV_SIZE 32768
126 #define PHYS_FLASH_1 (CFG_FLASH_BASE)
128 /*-----------------------------------------------------------------------
132 //#define CONFIG_PCI /* include pci support */
133 #undef CONFIG_PCI_PNP
134 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
137 #define CONFIG_EEPRO100
138 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
141 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
142 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
145 #define INTEGRATOR_PCI_BASE 0x40000000
146 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
148 // memory map as seen by the CPU on the local bus
149 #define CPU_PCI_IO_ADRS 0x60000000 // PCI I/O space base
150 #define CPU_PCI_IO_SIZE 0x10000
152 #define CPU_PCI_CNFG_ADRS 0x61000000 // PCI config space
153 #define CPU_PCI_CNFG_SIZE 0x1000000
155 #define PCI_MEM_BASE 0x40000000 // 512M to xxx
156 // unused 256M from A0000000-AFFFFFFF might be used for I2O ???
157 #define INTEGRATOR_PCI_IO_BASE 0x60000000 // 16M to xxx
158 // unused (128-16)M from B1000000-B7FFFFFF
159 #define PCI_CONFIG_BASE 0x61000000 // 16M to xxx
160 // unused ((128-16)M - 64K) from XXX
162 #define PCI_V3_BASE 0x62000000
164 // V3 PCI bridge controller
165 #define V3_BASE 0x62000000 // V360EPC registers
167 #define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS)
168 #define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
171 #define V3_PCI_VENDOR 0x00000000
172 #define V3_PCI_DEVICE 0x00000002
173 #define V3_PCI_CMD 0x00000004
174 #define V3_PCI_STAT 0x00000006
175 #define V3_PCI_CC_REV 0x00000008
176 #define V3_PCI_HDR_CF 0x0000000C
177 #define V3_PCI_IO_BASE 0x00000010
178 #define V3_PCI_BASE0 0x00000014
179 #define V3_PCI_BASE1 0x00000018
180 #define V3_PCI_SUB_VENDOR 0x0000002C
181 #define V3_PCI_SUB_ID 0x0000002E
182 #define V3_PCI_ROM 0x00000030
183 #define V3_PCI_BPARAM 0x0000003C
184 #define V3_PCI_MAP0 0x00000040
185 #define V3_PCI_MAP1 0x00000044
186 #define V3_PCI_INT_STAT 0x00000048
187 #define V3_PCI_INT_CFG 0x0000004C
188 #define V3_LB_BASE0 0x00000054
189 #define V3_LB_BASE1 0x00000058
190 #define V3_LB_MAP0 0x0000005E
191 #define V3_LB_MAP1 0x00000062
192 #define V3_LB_BASE2 0x00000064
193 #define V3_LB_MAP2 0x00000066
194 #define V3_LB_SIZE 0x00000068
195 #define V3_LB_IO_BASE 0x0000006E
196 #define V3_FIFO_CFG 0x00000070
197 #define V3_FIFO_PRIORITY 0x00000072
198 #define V3_FIFO_STAT 0x00000074
199 #define V3_LB_ISTAT 0x00000076
200 #define V3_LB_IMASK 0x00000077
201 #define V3_SYSTEM 0x00000078
202 #define V3_LB_CFG 0x0000007A
203 #define V3_PCI_CFG 0x0000007C
204 #define V3_DMA_PCI_ADR0 0x00000080
205 #define V3_DMA_PCI_ADR1 0x00000090
206 #define V3_DMA_LOCAL_ADR0 0x00000084
207 #define V3_DMA_LOCAL_ADR1 0x00000094
208 #define V3_DMA_LENGTH0 0x00000088
209 #define V3_DMA_LENGTH1 0x00000098
210 #define V3_DMA_CSR0 0x0000008B
211 #define V3_DMA_CSR1 0x0000009B
212 #define V3_DMA_CTLB_ADR0 0x0000008C
213 #define V3_DMA_CTLB_ADR1 0x0000009C
214 #define V3_DMA_DELAY 0x000000E0
215 #define V3_MAIL_DATA 0x000000C0
216 #define V3_PCI_MAIL_IEWR 0x000000D0
217 #define V3_PCI_MAIL_IERD 0x000000D2
218 #define V3_LB_MAIL_IEWR 0x000000D4
219 #define V3_LB_MAIL_IERD 0x000000D6
220 #define V3_MAIL_WR_STAT 0x000000D8
221 #define V3_MAIL_RD_STAT 0x000000DA
222 #define V3_QBA_MAP 0x000000DC
224 // SYSTEM register bits
225 #define V3_SYSTEM_M_RST_OUT (1 << 15)
226 #define V3_SYSTEM_M_LOCK (1 << 14)
229 #define V3_PCI_CFG_M_RETRY_EN (1 << 10)
230 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
231 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
233 // PCI MAP register bits (PCI -> Local bus)
234 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
235 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
236 #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
237 #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
238 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
239 #define V3_PCI_MAP_M_REG_EN (1 << 1)
240 #define V3_PCI_MAP_M_ENABLE (1 << 0)
242 // 9 => 512M window size
243 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
245 // A => 1024M window size
246 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
248 // LB_BASE register bits (Local bus -> PCI)
249 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000
250 #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
251 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0
252 #define V3_LB_BASE_M_PREFETCH (1 << 3)
253 #define V3_LB_BASE_M_ENABLE (1 << 0)
255 // PCI COMMAND REGISTER bits
256 #define V3_COMMAND_M_FBB_EN (1 << 9)
257 #define V3_COMMAND_M_SERR_EN (1 << 8)
258 #define V3_COMMAND_M_PAR_EN (1 << 6)
259 #define V3_COMMAND_M_MASTER_EN (1 << 2)
260 #define V3_COMMAND_M_MEM_EN (1 << 1)
261 #define V3_COMMAND_M_IO_EN (1 << 0)
263 #define INTEGRATOR_SC_BASE 0x11000000
264 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
265 #define INTEGRATOR_SC_PCIENABLE \
266 (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
269 #endif /* __CONFIG_H */