2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 * U-Boot:include/configs/da850evm.h
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 * Based on davinci_dvevm.h. Original Copyrights follow:
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12 * SPDX-License-Identifier: GPL-2.0+
21 #define CONFIG_DRIVER_TI_EMAC
26 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
27 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
28 #define CONFIG_SYS_OSCIN_FREQ 24000000
29 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
30 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
35 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
36 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
37 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
38 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
40 /* memtest start addr */
41 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
43 /* memtest will be run on 16MB */
44 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
46 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
48 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
49 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
50 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
51 DAVINCI_SYSCFG_SUSPSRC_UART0 | \
52 DAVINCI_SYSCFG_SUSPSRC_EMAC)
58 #define CONFIG_SYS_DA850_PLL0_PLLM 24
59 #define CONFIG_SYS_DA850_PLL1_PLLM 24
62 * DDR2 memory configuration
64 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
65 DV_DDR_PHY_EXT_STRBEN | \
66 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
67 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
69 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
70 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
72 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
73 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
74 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
75 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
76 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
77 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
78 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
79 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
80 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
82 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
83 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
84 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
85 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
86 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
87 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
88 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
89 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
91 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
92 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
93 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
94 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
95 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
96 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
97 (2 << DV_DDR_SDCR_CL_SHIFT) | \
98 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
99 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
101 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
102 DAVINCI_ABCR_WSTROBE(2) | \
103 DAVINCI_ABCR_WHOLD(0) | \
104 DAVINCI_ABCR_RSETUP(1) | \
105 DAVINCI_ABCR_RSTROBE(2) | \
106 DAVINCI_ABCR_RHOLD(1) | \
107 DAVINCI_ABCR_TA(0) | \
108 DAVINCI_ABCR_ASIZE_8BIT)
113 #define CONFIG_SYS_NS16550_SERIAL
114 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
115 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
116 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
119 * Flash & Environment
121 #define CONFIG_NAND_DAVINCI
122 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
123 #define CONFIG_ENV_SIZE (128 << 10)
124 #define CONFIG_SYS_NAND_USE_FLASH_BBT
125 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
126 #define CONFIG_SYS_NAND_PAGE_2K
127 #define CONFIG_SYS_NAND_CS 3
128 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
129 #define CONFIG_SYS_NAND_MASK_CLE 0x10
130 #define CONFIG_SYS_NAND_MASK_ALE 0x8
131 #undef CONFIG_SYS_NAND_HW_ECC
132 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
133 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
134 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
135 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
136 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
137 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
138 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
139 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
140 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
141 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
142 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
143 CONFIG_SYS_NAND_U_BOOT_SIZE - \
144 CONFIG_SYS_MALLOC_LEN - \
145 GENERATED_GBL_DATA_SIZE)
146 #define CONFIG_SYS_NAND_ECCPOS { \
147 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
148 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
149 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
150 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
151 #define CONFIG_SYS_NAND_PAGE_COUNT 64
152 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
153 #define CONFIG_SYS_NAND_ECCSIZE 512
154 #define CONFIG_SYS_NAND_ECCBYTES 10
155 #define CONFIG_SYS_NAND_OOBSIZE 64
156 #define CONFIG_SPL_NAND_BASE
157 #define CONFIG_SPL_NAND_DRIVERS
158 #define CONFIG_SPL_NAND_ECC
159 #define CONFIG_SPL_NAND_LOAD
162 * Network & Ethernet Configuration
164 #ifdef CONFIG_DRIVER_TI_EMAC
165 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
166 #define CONFIG_BOOTP_DEFAULT
167 #define CONFIG_BOOTP_DNS2
168 #define CONFIG_BOOTP_SEND_HOSTNAME
169 #define CONFIG_NET_RETRY_COUNT 10
173 * U-Boot general configuration
175 #define CONFIG_MISC_INIT_R
176 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
177 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
178 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
179 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
180 #define CONFIG_MX_CYCLIC
185 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
186 #define CONFIG_HWCONFIG /* enable hwconfig */
187 #define CONFIG_CMDLINE_TAG
188 #define CONFIG_REVISION_TAG
189 #define CONFIG_SETUP_MEMORY_TAGS
190 #define CONFIG_EXTRA_ENV_SETTINGS \
191 "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
192 "root=/dev/mtdblock5 rw noinitrd " \
193 "rootfstype=jffs2 noinitrd\0" \
194 "hwconfig=dsp:wake=yes\0" \
195 "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
196 "bootfile=uImage\0" \
197 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
198 "mtddevname=uboot-env\0" \
200 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
201 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
202 "u-boot=/tftpboot/ipam390/u-boot.ais\0" \
203 "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
204 "nand write c0000000 20000 ${filesize}\0" \
205 "setbootparms=nand read c0100000 200000 400000;" \
206 "run defbootargs addmtd;" \
207 "spl export atags c0100000;" \
208 "nand erase.part bootparms;" \
209 "nand write c0000100 180000 20000\0" \
212 #ifdef CONFIG_CMD_BDI
213 #define CONFIG_CLOCKS
216 #ifndef CONFIG_DRIVER_TI_EMAC
219 #define CONFIG_MTD_DEVICE
220 #define CONFIG_MTD_PARTITIONS
222 /* defines for SPL */
223 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
224 CONFIG_SYS_MALLOC_LEN)
225 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
226 #define CONFIG_SPL_STACK 0x8001ff00
227 #define CONFIG_SPL_TEXT_BASE 0x80000000
228 #define CONFIG_SPL_MAX_SIZE 0x20000
229 #define CONFIG_SPL_MAX_FOOTPRINT 32768
231 /* additions for new relocation code, must added to all boards */
232 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
234 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
235 GENERATED_GBL_DATA_SIZE)
237 /* add FALCON boot mode */
238 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
239 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
242 #define CONFIG_DA8XX_GPIO
243 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
245 #define CONFIG_SHOW_BOOT_PROGRESS
246 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
247 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
249 #include <asm/arch/hardware.h>
251 #endif /* __CONFIG_H */