2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 * U-Boot:include/configs/da850evm.h
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 * Based on davinci_dvevm.h. Original Copyrights follow:
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12 * SPDX-License-Identifier: GPL-2.0+
21 #define CONFIG_DRIVER_TI_EMAC
22 #define CONFIG_BARIX_IPAM390
27 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
28 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
29 #define CONFIG_SYS_OSCIN_FREQ 24000000
30 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
31 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
32 #define CONFIG_SYS_TEXT_BASE 0xc1080000
37 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
38 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
39 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
40 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
42 /* memtest start addr */
43 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
45 /* memtest will be run on 16MB */
46 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
48 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
50 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
51 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
52 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
53 DAVINCI_SYSCFG_SUSPSRC_UART0 | \
54 DAVINCI_SYSCFG_SUSPSRC_EMAC)
59 #define CONFIG_SYS_DV_CLKMODE 0
60 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
61 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
62 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
63 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
64 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
65 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
66 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
69 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
70 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
71 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
72 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
74 #define CONFIG_SYS_DA850_PLL0_PLLM 24
75 #define CONFIG_SYS_DA850_PLL1_PLLM 24
78 * DDR2 memory configuration
80 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
81 DV_DDR_PHY_EXT_STRBEN | \
82 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
83 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
85 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
86 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
88 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
89 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
90 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
91 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
92 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
93 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
94 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
95 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
96 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
98 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
99 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
100 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
101 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
102 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
103 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
104 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
105 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
107 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
108 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
109 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
110 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
111 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
112 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
113 (2 << DV_DDR_SDCR_CL_SHIFT) | \
114 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
115 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
117 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
118 DAVINCI_ABCR_WSTROBE(2) | \
119 DAVINCI_ABCR_WHOLD(0) | \
120 DAVINCI_ABCR_RSETUP(1) | \
121 DAVINCI_ABCR_RSTROBE(2) | \
122 DAVINCI_ABCR_RHOLD(1) | \
123 DAVINCI_ABCR_TA(0) | \
124 DAVINCI_ABCR_ASIZE_8BIT)
129 #define CONFIG_SYS_NS16550_SERIAL
130 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
131 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
132 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
133 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
136 * Flash & Environment
138 #define CONFIG_NAND_DAVINCI
139 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
140 #define CONFIG_ENV_SIZE (128 << 10)
141 #define CONFIG_SYS_NAND_USE_FLASH_BBT
142 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
143 #define CONFIG_SYS_NAND_PAGE_2K
144 #define CONFIG_SYS_NAND_CS 3
145 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
146 #define CONFIG_SYS_NAND_MASK_CLE 0x10
147 #define CONFIG_SYS_NAND_MASK_ALE 0x8
148 #undef CONFIG_SYS_NAND_HW_ECC
149 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
150 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
151 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
152 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
153 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
154 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
155 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
156 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
157 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
158 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
159 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
160 CONFIG_SYS_NAND_U_BOOT_SIZE - \
161 CONFIG_SYS_MALLOC_LEN - \
162 GENERATED_GBL_DATA_SIZE)
163 #define CONFIG_SYS_NAND_ECCPOS { \
164 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
165 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
166 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
167 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
168 #define CONFIG_SYS_NAND_PAGE_COUNT 64
169 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
170 #define CONFIG_SYS_NAND_ECCSIZE 512
171 #define CONFIG_SYS_NAND_ECCBYTES 10
172 #define CONFIG_SYS_NAND_OOBSIZE 64
173 #define CONFIG_SPL_NAND_BASE
174 #define CONFIG_SPL_NAND_DRIVERS
175 #define CONFIG_SPL_NAND_ECC
176 #define CONFIG_SPL_NAND_LOAD
179 * Network & Ethernet Configuration
181 #ifdef CONFIG_DRIVER_TI_EMAC
182 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
183 #define CONFIG_BOOTP_DEFAULT
184 #define CONFIG_BOOTP_DNS
185 #define CONFIG_BOOTP_DNS2
186 #define CONFIG_BOOTP_SEND_HOSTNAME
187 #define CONFIG_NET_RETRY_COUNT 10
191 * U-Boot general configuration
193 #define CONFIG_MISC_INIT_R
194 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
195 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
196 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
197 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
198 #define CONFIG_AUTO_COMPLETE
199 #define CONFIG_CMDLINE_EDITING
200 #define CONFIG_SYS_LONGHELP
201 #define CONFIG_MX_CYCLIC
206 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
207 #define CONFIG_HWCONFIG /* enable hwconfig */
208 #define CONFIG_CMDLINE_TAG
209 #define CONFIG_REVISION_TAG
210 #define CONFIG_SETUP_MEMORY_TAGS
211 #define CONFIG_EXTRA_ENV_SETTINGS \
212 "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
213 "root=/dev/mtdblock5 rw noinitrd " \
214 "rootfstype=jffs2 noinitrd\0" \
215 "hwconfig=dsp:wake=yes\0" \
216 "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
217 "bootfile=uImage\0" \
218 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
219 "mtddevname=uboot-env\0" \
221 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
222 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
223 "u-boot=/tftpboot/ipam390/u-boot.ais\0" \
224 "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
225 "nand write c0000000 20000 ${filesize}\0" \
226 "setbootparms=nand read c0100000 200000 400000;" \
227 "run defbootargs addmtd;" \
228 "spl export atags c0100000;" \
229 "nand erase.part bootparms;" \
230 "nand write c0000100 180000 20000\0" \
233 #ifdef CONFIG_CMD_BDI
234 #define CONFIG_CLOCKS
237 #ifndef CONFIG_DRIVER_TI_EMAC
240 #define CONFIG_MTD_DEVICE
241 #define CONFIG_MTD_PARTITIONS
243 /* defines for SPL */
244 #define CONFIG_SPL_FRAMEWORK
245 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
246 CONFIG_SYS_MALLOC_LEN)
247 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
248 #define CONFIG_SPL_STACK 0x8001ff00
249 #define CONFIG_SPL_TEXT_BASE 0x80000000
250 #define CONFIG_SPL_MAX_SIZE 0x20000
251 #define CONFIG_SPL_MAX_FOOTPRINT 32768
253 /* additions for new relocation code, must added to all boards */
254 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
256 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
257 GENERATED_GBL_DATA_SIZE)
259 /* add FALCON boot mode */
260 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
261 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
264 #define CONFIG_DA8XX_GPIO
265 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
267 #define CONFIG_SHOW_BOOT_PROGRESS
268 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
269 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
271 #include <asm/arch/hardware.h>
273 #endif /* __CONFIG_H */