6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
15 * High Level Configuration Options
18 #define CONFIG_MPC5200
19 #define CONFIG_MPX5200 1 /* MPX5200 board */
20 #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
21 #define CONFIG_IPEK01 /* Motherboard is ipek01 */
23 #define CONFIG_SYS_TEXT_BASE 0xfc000000
25 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
27 #define CONFIG_MISC_INIT_R
29 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
30 #ifdef CONFIG_CMD_KGDB
31 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
35 * Serial console configuration
37 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
38 #define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
39 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
41 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
44 * Video configuration for LIME GDC
47 #define CONFIG_VIDEO_MB862xx
48 #define CONFIG_VIDEO_MB862xx_ACCEL
49 #define VIDEO_FB_16BPP_WORD_SWAP
50 #define CONFIG_CFB_CONSOLE
51 #define CONFIG_VIDEO_LOGO
52 #define CONFIG_VIDEO_BMP_LOGO
53 #define CONFIG_CONSOLE_EXTRA_INFO
54 #define CONFIG_VGA_AS_SINGLE_DEVICE
55 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
56 #define CONFIG_VIDEO_SW_CURSOR
57 #define CONFIG_SPLASH_SCREEN
58 #define CONFIG_VIDEO_BMP_GZIP
59 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
60 /* Lime clock frequency */
61 #define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
63 #define CONFIG_SYS_MB862xx_MMR 0x41c767e3
68 * 0x40000000 - 0x4fffffff - PCI Memory
69 * 0x50000000 - 0x50ffffff - PCI IO Space
72 #define CONFIG_PCI_PNP 1
73 #define CONFIG_PCI_SCAN_SHOW 1
75 #define CONFIG_PCI_MEM_BUS 0x40000000
76 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
77 #define CONFIG_PCI_MEM_SIZE 0x10000000
79 #define CONFIG_PCI_IO_BUS 0x50000000
80 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
81 #define CONFIG_PCI_IO_SIZE 0x01000000
84 #define CONFIG_EEPRO100 1
85 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
88 #define CONFIG_DOS_PARTITION
91 #define CONFIG_USB_OHCI_NEW
92 #define CONFIG_SYS_OHCI_BE_CONTROLLER
94 #define CONFIG_SYS_USB_OHCI_CPU_INIT
95 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
96 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
97 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
100 * Command line configuration.
103 #define CONFIG_CMD_BMP /* BMP support */
105 #define CONFIG_CMD_DATE /* support for RTC, date/time...*/
106 #define CONFIG_CMD_IDE /* IDE harddisk support */
107 #define CONFIG_CMD_IRQ /* irqinfo */
108 #define CONFIG_CMD_PCI /* pciinfo */
110 #define CONFIG_SYS_LOWBOOT 1
116 #define CONFIG_PREBOOT "echo;" \
117 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
120 #undef CONFIG_BOOTARGS
122 #define CONFIG_EXTRA_ENV_SETTINGS \
124 "consoledev=ttyPSC0\0" \
125 "hostname=ipek01\0" \
126 "nfsargs=setenv bootargs root=/dev/nfs rw " \
127 "nfsroot=${serverip}:${rootpath}\0" \
128 "ramargs=setenv bootargs root=/dev/ram rw\0" \
129 "addip=setenv bootargs ${bootargs} " \
130 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
131 ":${hostname}:${netdev}:off panic=1\0" \
132 "addtty=setenv bootargs ${bootargs} " \
133 "console=${consoledev},${baudrate}\0" \
134 "flash_nfs=run nfsargs addip addtty;" \
135 "bootm ${kernel_addr} - ${fdtaddr}\0" \
136 "flash_self=run ramargs addip addtty;" \
137 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
138 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
139 "run nfsargs addip addtty;" \
140 "bootm ${loadaddr} - ${fdtaddr}\0" \
141 "rootpath=/opt/eldk/ppc_6xx\0" \
142 "bootfile=ipek01/uImage\0" \
143 "load=tftp 100000 ipek01/u-boot.bin\0" \
144 "update=protect off FC000000 +60000; era FC000000 +60000; " \
145 "cp.b 100000 FC000000 ${filesize}\0" \
146 "upd=run load;run update\0" \
148 "loadaddr=400000\0" \
149 "fdtfile=ipek01/ipek01.dtb\0" \
152 #define CONFIG_BOOTCOMMAND "run flash_self"
155 * IPB Bus clocking configuration.
157 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
158 /* PCI clock must be 33, because board will not boot */
159 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
162 * Open firmware flat tree support
164 #define OF_CPU "PowerPC,5200@0"
165 #define OF_SOC "soc5200@f0000000"
166 #define OF_TBCLK (bd->bi_busfreq / 4)
171 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
172 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
174 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
175 #define CONFIG_SYS_I2C_SLAVE 0x7F
178 * EEPROM configuration
180 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
188 #define CONFIG_RTC_PCF8563
189 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
191 #define CONFIG_SYS_FLASH_BASE 0xFC000000
192 #define CONFIG_SYS_FLASH_SIZE 0x01000000
193 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
194 CONFIG_SYS_MONITOR_LEN)
196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
197 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
198 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
200 /* use CFI flash driver */
201 #define CONFIG_FLASH_CFI_DRIVER
202 #define CONFIG_SYS_FLASH_CFI
203 #define CONFIG_SYS_FLASH_EMPTY_INFO
204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
207 * Environment settings
209 #define CONFIG_ENV_IS_IN_FLASH 1
210 #define CONFIG_ENV_SIZE 0x10000
211 #define CONFIG_ENV_SECT_SIZE 0x20000
212 #define CONFIG_ENV_OVERWRITE 1
213 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
214 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
219 #define CONFIG_SYS_MBAR 0xf0000000
220 #define CONFIG_SYS_SDRAM_BASE 0x00000000
221 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
222 #define CONFIG_SYS_SRAM_BASE 0xF1000000
223 #define CONFIG_SYS_SRAM_SIZE 0x00200000
224 #define CONFIG_SYS_LIME_BASE 0xE4000000
225 #define CONFIG_SYS_LIME_SIZE 0x04000000
226 #define CONFIG_SYS_FPGA_BASE 0xC0000000
227 #define CONFIG_SYS_FPGA_SIZE 0x10000000
228 #define CONFIG_SYS_MPEG_BASE 0xe2000000
229 #define CONFIG_SYS_MPEG_SIZE 0x01000000
230 #define CONFIG_SYS_CF_BASE 0xe1000000
231 #define CONFIG_SYS_CF_SIZE 0x01000000
233 /* Use SRAM until RAM will be available */
234 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
235 /* End of used area in DPRAM */
236 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
239 GENERATED_GBL_DATA_SIZE)
240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
243 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
244 # define CONFIG_SYS_RAMBOOT 1
247 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
248 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
249 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
252 * Ethernet configuration
254 #define CONFIG_MPC5xxx_FEC 1
255 #define CONFIG_MPC5xxx_FEC_MII100
256 #define CONFIG_PHY_ADDR 0x00
261 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
264 * Miscellaneous configurable options
266 #define CONFIG_SYS_LONGHELP /* undef to save memory */
267 #ifdef CONFIG_CMD_KGDB
268 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
270 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
272 /* Print Buffer Size */
273 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
274 sizeof(CONFIG_SYS_PROMPT) + 16)
275 /* max number of command args */
276 #define CONFIG_SYS_MAXARGS 16
277 /* Boot Argument Buffer Size */
278 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
280 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
281 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
283 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
286 * Various low-level settings
288 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
289 #define CONFIG_SYS_HID0_FINAL HID0_ICE
291 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
292 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
293 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
294 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
295 #define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
296 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
297 #define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
298 #define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
299 #define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
300 #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
301 #define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
302 #define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
303 #define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
304 #define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
306 #ifdef CONFIG_SYS_PCISPEED_66
307 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
308 #define CONFIG_SYS_CS1_CFG 0x0004FB00
309 #define CONFIG_SYS_CS2_CFG 0x0006F900
311 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
312 #define CONFIG_SYS_CS1_CFG 0x0001FB00
313 #define CONFIG_SYS_CS2_CFG 0x0002F90C
317 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
318 * waitstates, writeswap and readswap enabled
320 #define CONFIG_SYS_CS3_CFG 0x00FFFB0C
321 #define CONFIG_SYS_CS6_CFG 0x00FFFB0C
322 #define CONFIG_SYS_CS7_CFG 0x4040751C
324 #define CONFIG_SYS_CS_BURST 0x00000000
325 #define CONFIG_SYS_CS_DEADCYCLE 0x33330000
327 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
329 /*-----------------------------------------------------------------------
331 *-----------------------------------------------------------------------
333 #define CONFIG_USB_CLOCK 0x0001BBBB
334 #define CONFIG_USB_CONFIG 0x00005000
336 /*-----------------------------------------------------------------------
337 * IDE/ATA stuff Supports IDE harddisk
338 *-----------------------------------------------------------------------
340 #define CONFIG_IDE_PREINIT
342 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
343 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
345 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
347 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
349 /* Offset for data I/O */
350 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
352 /* Offset for normal register accesses */
353 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
355 /* Offset for alternate registers */
356 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
358 /* Interval between registers */
359 #define CONFIG_SYS_ATA_STRIDE 4
361 #endif /* __CONFIG_H */