3 * Matthias Weisser <weisserm@arcor.de>
5 * Configuation settings for the jadecpu board
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define CONFIG_MB86R0x
30 #define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
31 #define CONFIG_SYS_HZ 1000
32 #define CONFIG_SYS_TEXT_BASE 0x10000000
34 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
36 #define CONFIG_USE_ARCH_MEMCPY
37 #define CONFIG_USE_ARCH_MEMSET
39 #define MACH_TYPE_JADECPU 2636
41 #define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
44 * Environment settings
46 #define CONFIG_EXTRA_ENV_SETTINGS \
47 "gs_fast_boot=setenv bootdelay 5\0" \
48 "gs_slow_boot=setenv bootdelay 10\0" \
49 "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
50 "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
51 "bootelf 0x40000000\0" \
54 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
55 #define CONFIG_SETUP_MEMORY_TAGS 1
56 #define CONFIG_INITRD_TAG 1
57 #define CONFIG_BOARD_LATE_INIT
71 #define CONFIG_SERIAL_MULTI
72 #define CONFIG_SYS_NS16550
73 #define CONFIG_SYS_NS16550_SERIAL
74 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
75 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
76 #define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
77 #define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
78 #define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
79 #define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
81 #define CONFIG_CONS_INDEX 4
86 #define CONFIG_SMC911X
87 #define CONFIG_SMC911X_BASE 0x02000000
88 #define CONFIG_SMC911X_16_BIT
94 #define CONFIG_VIDEO_MB86R0xGDC
95 #define CONFIG_SYS_WHITE_ON_BLACK
96 #define CONFIG_CFB_CONSOLE
97 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
98 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
99 #define CONFIG_VIDEO_LOGO
100 #define CONFIG_SPLASH_SCREEN
101 #define CONFIG_SPLASH_SCREEN_ALIGN
102 #define CONFIG_VIDEO_BMP_LOGO
103 #define CONFIG_VIDEO_BMP_GZIP
104 #define CONFIG_VIDEO_BMP_RLE8
105 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
106 #define VIDEO_FB_16BPP_WORD_SWAP
107 #define VIDEO_KBD_INIT_FCT 0
108 #define VIDEO_TSTC_FCT serial_tstc
109 #define VIDEO_GETC_FCT serial_getc
114 #define CONFIG_BOOTP_BOOTFILESIZE 1
115 #define CONFIG_BOOTP_BOOTPATH 1
116 #define CONFIG_BOOTP_GATEWAY 1
117 #define CONFIG_BOOTP_HOSTNAME 1
120 * Command line configuration.
122 #include <config_cmd_default.h>
123 #undef CONFIG_CMD_BDI
124 #undef CONFIG_CMD_FPGA
125 #undef CONFIG_CMD_IMLS
126 #undef CONFIG_CMD_LOADS
127 #undef CONFIG_CMD_SOURCE
128 #undef CONFIG_CMD_NFS
129 #undef CONFIG_CMD_XIMG
131 #define CONFIG_CMD_BMP
132 #define CONFIG_CMD_DHCP
133 #define CONFIG_CMD_ELF
134 #define CONFIG_CMD_FAT
135 #define CONFIG_CMD_PING
136 #define CONFIG_CMD_USB
137 #define CONFIG_CMD_CACHE
139 #define CONFIG_SYS_HUSH_PARSER
142 #define CONFIG_USB_OHCI_NEW
143 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
144 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
145 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
146 #define CONFIG_USB_STORAGE
147 #define CONFIG_DOS_PARTITION
150 #define CONFIG_NR_DRAM_BANKS 1
151 #define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
152 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
154 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
155 #define CONFIG_SYS_INIT_SP_ADDR 0x01008000
158 * FLASH and environment organization
160 #define CONFIG_SYS_FLASH_BASE 0x10000000
161 #define CONFIG_SYS_MAX_FLASH_BANKS 1
162 #define CONFIG_SYS_MAX_FLASH_SECT 256
163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
165 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
166 #define CONFIG_ENV_IS_IN_FLASH 1
167 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
168 #define CONFIG_ENV_SIZE (128 * 1024)
171 * CFI FLASH driver setup
173 #define CONFIG_SYS_FLASH_CFI 1
174 #define CONFIG_FLASH_CFI_DRIVER 1
175 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
177 #define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
179 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
180 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
182 #define CONFIG_BAUDRATE 115200
184 #define CONFIG_SYS_PROMPT "jade> "
185 #define CONFIG_SYS_CBSIZE 256
186 #define CONFIG_SYS_MAXARGS 16
187 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
188 sizeof(CONFIG_SYS_PROMPT) + 16)
189 #define CONFIG_SYS_LONGHELP 1
190 #define CONFIG_CMDLINE_EDITING 1
192 #define CONFIG_PREBOOT ""
194 #define CONFIG_BOOTDELAY 5
195 #define CONFIG_AUTOBOOT_KEYED
196 #define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
197 #define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
198 #define CONFIG_AUTOBOOT_STOP_STR "stopgs"
201 * Size of malloc() pool
203 #define CONFIG_SYS_MALLOC_LEN (10 << 20)
204 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
207 * Clock reset generator init
209 #define CONFIG_SYS_CRG_CRHA_INIT 0xffff
210 #define CONFIG_SYS_CRG_CRPA_INIT 0xffff
211 #define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
212 #define CONFIG_SYS_CRG_CRHB_INIT 0xffff
213 #define CONFIG_SYS_CRG_CRAM_INIT 0xffef
216 * Memory controller settings
218 #define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
219 #define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
220 #define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
221 #define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
222 #define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
223 #define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
224 #define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
225 #define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
226 #define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
229 * DDR2 controller init settings
231 #define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
232 #define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
233 #define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
234 #define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
235 #define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
236 #define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
237 #define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
238 #define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
239 #define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
240 #define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
241 #define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
242 #define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
243 #define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
244 #define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
245 #define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
246 #define CONFIG_SYS_DDR2_DROS_INIT 0x0001
253 #define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
254 #define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
257 #define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
258 #define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
261 #define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
262 #define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
265 #define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
266 #define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
269 #define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
270 #define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
273 #define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
274 #define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
277 #define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
278 #define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
281 #define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
282 #define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
285 #define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
286 #define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
289 #define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
290 #define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
292 #endif /* __CONFIG_H */