3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* especially an MPC5200 */
34 #define CONFIG_JUPITER 1 /* ... on Jupiter board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define CONFIG_BOARD_EARLY_INIT_R 1
39 #define CONFIG_BOARD_EARLY_INIT_F 1
41 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42 #define BOOTFLAG_WARM 0x02 /* Software reboot */
45 * Serial console configuration
47 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
48 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
49 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
53 * 0x40000000 - 0x4fffffff - PCI Memory
54 * 0x50000000 - 0x50ffffff - PCI IO Space
56 /*#define CONFIG_PCI */
58 #if defined(CONFIG_PCI)
59 #define CONFIG_PCI_PNP 1
60 #define CONFIG_PCI_SCAN_SHOW 1
62 #define CONFIG_PCI_MEM_BUS 0x40000000
63 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
64 #define CONFIG_PCI_MEM_SIZE 0x10000000
66 #define CONFIG_PCI_IO_BUS 0x50000000
67 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
68 #define CONFIG_PCI_IO_SIZE 0x01000000
69 #define ADD_PCI_CMD CFG_CMD_PCI
72 #define CFG_XLB_PIPELINING 1
74 #define CONFIG_NET_MULTI 1
76 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
79 #define CONFIG_MAC_PARTITION
80 #define CONFIG_DOS_PARTITION
81 #define CONFIG_ISO_PARTITION
83 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
87 * Command line configuration.
89 #include <config_cmd_default.h>
91 #define CONFIG_CMD_NFS
92 #define CONFIG_CMD_SNTP
98 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
100 #define CONFIG_PREBOOT "echo;" \
101 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
104 #undef CONFIG_BOOTARGS
106 #define CONFIG_EXTRA_ENV_SETTINGS \
108 "nfsargs=setenv bootargs root=/dev/nfs rw " \
109 "nfsroot=${serverip}:${rootpath}\0" \
110 "ramargs=setenv bootargs root=/dev/ram rw\0" \
111 "addip=setenv bootargs ${bootargs} " \
112 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
113 ":${hostname}:${netdev}:off panic=1\0" \
114 "flash_nfs=run nfsargs addip addcons;" \
115 "bootm ${kernel_addr}\0" \
116 "flash_self=run ramargs addip;" \
117 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
118 "addcons=setenv bootargs ${bootargs} console=${contyp}," \
121 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
123 "rootpath=/opt/eldk/ppc_6xx\0" \
124 "bootfile=/tftpboot/jupiter/uImage\0" \
127 #define CONFIG_BOOTCOMMAND "run flash_self"
130 * IPB Bus clocking configuration.
132 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
135 /* pass open firmware flat tree */
136 #define CONFIG_OF_FLAT_TREE 1
137 #define CONFIG_OF_BOARD_SETUP 1
139 /* maximum size of the flat tree (8K) */
140 #define OF_FLAT_TREE_MAX_SIZE 8192
142 #define OF_CPU "PowerPC,5200@0"
143 #define OF_SOC "soc5200@f0000000"
144 #define OF_TBCLK (bd->bi_busfreq / 8)
145 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
152 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
153 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
155 #define CFG_I2C_SPEED 100000 /* 100 kHz */
156 #define CFG_I2C_SLAVE 0x7F
159 * EEPROM configuration
161 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
162 #define CFG_I2C_EEPROM_ADDR_LEN 1
163 #define CFG_EEPROM_PAGE_WRITE_BITS 3
164 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
168 * Flash configuration
170 #define CFG_FLASH_BASE 0xFF000000
171 #define CFG_FLASH_SIZE 0x01000000
173 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
175 #define CFG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */
177 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
178 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
180 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
182 #define CFG_FLASH_CFI_DRIVER
183 #define CFG_FLASH_CFI
184 #define CFG_FLASH_EMPTY_INFO
185 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
186 #define CFG_UPDATE_FLASH_SIZE 1
187 #define CFG_FLASH_USE_BUFFER_WRITE 1
190 * Environment settings
192 #define CFG_ENV_IS_IN_FLASH 1
193 #define CFG_ENV_SIZE 0x20000
194 #define CFG_ENV_SECT_SIZE 0x20000
195 #define CONFIG_ENV_OVERWRITE 1
197 /* Address and size of Redundant Environment Sector */
198 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
199 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
204 #define CFG_MBAR 0xF0000000
205 #define CFG_SDRAM_BASE 0x00000000
206 #define CFG_DEFAULT_MBAR 0x80000000
208 /* Use SRAM until RAM will be available */
209 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
210 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
213 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
214 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
215 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
217 #define CFG_MONITOR_BASE TEXT_BASE
218 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
219 # define CFG_RAMBOOT 1
222 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
223 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
224 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
227 * Ethernet configuration
229 #define CONFIG_MPC5xxx_FEC 1
231 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
233 /* #define CONFIG_FEC_10MBIT 1 */
234 #define CONFIG_PHY_ADDR 0x00
239 #define CFG_GPS_PORT_CONFIG 0x10000004
242 * Miscellaneous configurable options
244 #define CFG_LONGHELP /* undef to save memory */
245 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
247 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
248 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
249 #ifdef CFG_HUSH_PARSER
250 #define CFG_PROMPT_HUSH_PS2 "> "
252 #if defined(CONFIG_CMD_KGDB)
253 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
255 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
257 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
258 #define CFG_MAXARGS 16 /* max number of command args */
259 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
261 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
262 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
263 #define CFG_ALT_MEMTEST 1
265 #define CFG_LOAD_ADDR 0x200000 /* default load address */
267 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
269 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
270 #if defined(CONFIG_CMD_KGDB)
271 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
275 * Various low-level settings
277 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
278 #define CFG_HID0_FINAL HID0_ICE
280 #define CFG_BOOTCS_START CFG_FLASH_BASE
281 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
282 #define CFG_BOOTCS_CFG 0x00047801
283 #define CFG_CS0_START CFG_FLASH_BASE
284 #define CFG_CS0_SIZE CFG_FLASH_SIZE
286 #define CFG_CS_BURST 0x00000000
287 #define CFG_CS_DEADCYCLE 0x33333333
289 #define CFG_RESET_ADDRESS 0xff000000
291 #endif /* __CONFIG_H */