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1 /*
2  * Copyright (c) 2008 Nuovation System Designs, LLC
3  *   Grant Erickson <gerickson@nuovations.com>
4  *
5  * (C) Copyright 2007
6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 /************************************************************************
12  * kilauea.h - configuration for AMCC Kilauea (405EX)
13  ***********************************************************************/
14
15 #ifndef __CONFIG_H
16 #define __CONFIG_H
17
18 /*-----------------------------------------------------------------------
19  * High Level Configuration Options
20  *----------------------------------------------------------------------*/
21 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
22 #define CONFIG_405EX            1               /* Specifc 405EX support*/
23 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
24
25 #ifndef CONFIG_SYS_TEXT_BASE
26 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
27 #endif
28
29 /*
30  * CHIP_21 errata - you must set this to match your exact CPU, else your
31  * board will not boot.  DO NOT enable this unless you have JTAG available
32  * for recovery, in the event you get it wrong.
33  *
34  * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
35  * may be equipped for security or not.  You must look at the CPU part
36  * number to be sure what you have.
37  */
38 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
39 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
40 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
41 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
42
43 /*
44  * Include common defines/options for all AMCC eval boards
45  */
46 #define CONFIG_HOSTNAME         kilauea
47 #include "amcc-common.h"
48
49 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
50 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
51 #define CONFIG_BOARD_TYPES
52 #define CONFIG_BOARD_EMAC_COUNT
53
54 /*-----------------------------------------------------------------------
55  * Base addresses -- Note these are effective addresses where the
56  * actual resources get mapped (not physical addresses)
57  *----------------------------------------------------------------------*/
58 #define CONFIG_SYS_FLASH_BASE           0xFC000000
59 #define CONFIG_SYS_NAND_ADDR            0xF8000000
60 #define CONFIG_SYS_FPGA_BASE            0xF0000000
61
62 /*-----------------------------------------------------------------------
63  * Initial RAM & Stack Pointer Configuration Options
64  *
65  *   There are traditionally three options for the primordial
66  *   (i.e. initial) stack usage on the 405-series:
67  *
68  *      1) On-chip Memory (OCM) (i.e. SRAM)
69  *      2) Data cache
70  *      3) SDRAM
71  *
72  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
73  *   the latter of which is less than desireable since it requires
74  *   setting up the SDRAM and ECC in assembly code.
75  *
76  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
77  *   select on the External Bus Controller (EBC) and then select a
78  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
79  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
80  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
81  *   physical SDRAM to use (3).
82  *-----------------------------------------------------------------------*/
83
84 #define CONFIG_SYS_INIT_DCACHE_CS       4
85
86 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
87 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
88 #else
89 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
90 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
91
92 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
93 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
94
95 /*
96  * If the data cache is being used for the primordial stack and global
97  * data area, the POST word must be placed somewhere else. The General
98  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
99  * its compare and mask register contents across reset, so it is used
100  * for the POST word.
101  */
102
103 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
104 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
105 # define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
106 #else
107 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
108 # define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
109 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
110 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
111
112 /*-----------------------------------------------------------------------
113  * Serial Port
114  *----------------------------------------------------------------------*/
115 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
116 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
117
118 /*-----------------------------------------------------------------------
119  * Environment
120  *----------------------------------------------------------------------*/
121 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
122
123 /*-----------------------------------------------------------------------
124  * FLASH related
125  *----------------------------------------------------------------------*/
126 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
127 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
128
129 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
130 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
131 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
132
133 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
134 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
135
136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
137 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
138
139 #ifdef CONFIG_ENV_IS_IN_FLASH
140 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
141 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
142 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
143
144 /* Address and size of Redundant Environment Sector     */
145 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
146 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
147 #endif /* CONFIG_ENV_IS_IN_FLASH */
148
149 /*-----------------------------------------------------------------------
150  * NAND FLASH
151  *----------------------------------------------------------------------*/
152 #define CONFIG_SYS_MAX_NAND_DEVICE      1
153 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
154 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
155
156 /*-----------------------------------------------------------------------
157  * DDR SDRAM
158  *----------------------------------------------------------------------*/
159 #define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
160
161 /*
162  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
163  *
164  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
165  *       SDRAM Controller DDR autocalibration values and takes a lot longer
166  *       to run than Method_B.
167  * (See the Method_A and Method_B algorithm discription in the file:
168  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
169  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
170  *
171  * DDR Autocalibration Method_B is the default.
172  */
173 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
174 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
175 #undef  CONFIG_PPC4xx_DDR_METHOD_A
176
177 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
178
179 /* DDR1/2 SDRAM Device Control Register Data Values */
180 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
181                                  SDRAM_RXBAS_SDSZ_256MB         | \
182                                  SDRAM_RXBAS_SDAM_MODE7         | \
183                                  SDRAM_RXBAS_SDBE_ENABLE)
184 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
185 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
186 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
187 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
188                                  SDRAM_MCOPT1_8_BANKS           | \
189                                  SDRAM_MCOPT1_DDR2_TYPE         | \
190                                  SDRAM_MCOPT1_QDEP              | \
191                                  SDRAM_MCOPT1_DCOO_DISABLED)
192 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
193 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
194                                  SDRAM_MODT_EB0R_ENABLE)
195 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
196 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
197                                  SDRAM_CODT_CKLZ_36OHM          | \
198                                  SDRAM_CODT_DQS_1_8_V_DDR2      | \
199                                  SDRAM_CODT_IO_NMODE)
200 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
201 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
202                 SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
203                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
204 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
205                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
206                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
207                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
208                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
209 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
210                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
211                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
212                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
213                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
214 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
215                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
216                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
217                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
218                 SDRAM_INITPLR_IMA_ENCODE(0))
219 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
220                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
221                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
222                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
223                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
224                                          JEDEC_MA_EMR_RTT_75OHM))
225 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
226                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
227                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
228                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
229                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
230                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
231                                          JEDEC_MA_MR_BLEN_4 | \
232                                          JEDEC_MA_MR_DLL_RESET))
233 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
234                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
235                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
236                 SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
237                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
238 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
239                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
240                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
241 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
242                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
243                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
244 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
245                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
246                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
247 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
248                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
249                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
250 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
251                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
252                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
253                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
254                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
255                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
256                                          JEDEC_MA_MR_BLEN_4))
257 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
258                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
259                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
260                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
261                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
262                                          JEDEC_MA_EMR_RDQS_DISABLE | \
263                                          JEDEC_MA_EMR_DQS_DISABLE | \
264                                          JEDEC_MA_EMR_RTT_DISABLED | \
265                                          JEDEC_MA_EMR_ODS_NORMAL))
266 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
267                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
268                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
269                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
270                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
271                                          JEDEC_MA_EMR_RDQS_DISABLE | \
272                                          JEDEC_MA_EMR_DQS_DISABLE | \
273                                          JEDEC_MA_EMR_RTT_DISABLED | \
274                                          JEDEC_MA_EMR_ODS_NORMAL))
275 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
276 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
277 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
278                                  SDRAM_RQDC_RQFD_ENCODE(56))
279 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
280 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
281 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
282                                  SDRAM_DLCR_DLCS_CONT_DONE      | \
283                                  SDRAM_DLCR_DLCV_ENCODE(165))
284 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
285 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
286 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
287                                  SDRAM_SDTR1_RTW_2_CLK  | \
288                                  SDRAM_SDTR1_RTRO_1_CLK)
289 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
290                                  SDRAM_SDTR2_WTR_2_CLK          | \
291                                  SDRAM_SDTR2_XSNR_32_CLK        | \
292                                  SDRAM_SDTR2_WPC_4_CLK          | \
293                                  SDRAM_SDTR2_RPC_2_CLK          | \
294                                  SDRAM_SDTR2_RP_3_CLK           | \
295                                  SDRAM_SDTR2_RRD_2_CLK)
296 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
297                                  SDRAM_SDTR3_RC_ENCODE(11)      | \
298                                  SDRAM_SDTR3_XCS                | \
299                                  SDRAM_SDTR3_RFC_ENCODE(26))
300 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
301                                  SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
302                                  SDRAM_MMODE_BLEN_4)
303 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
304                                  SDRAM_MEMODE_RTT_75OHM)
305
306 /*-----------------------------------------------------------------------
307  * I2C
308  *----------------------------------------------------------------------*/
309 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
310
311 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
312 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
315
316 /* I2C bootstrap EEPROM */
317 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
318 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
319 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
320
321 /* Standard DTT sensor configuration */
322 #define CONFIG_DTT_DS1775       1
323 #define CONFIG_DTT_SENSORS      { 0 }
324 #define CONFIG_SYS_I2C_DTT_ADDR 0x48
325
326 /* RTC configuration */
327 #define CONFIG_RTC_DS1338       1
328 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
329
330 /*-----------------------------------------------------------------------
331  * Ethernet
332  *----------------------------------------------------------------------*/
333 #define CONFIG_M88E1111_PHY     1
334 #define CONFIG_IBM_EMAC4_V4     1
335 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
336 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
337
338 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
339 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
340
341 #define CONFIG_HAS_ETH0         1
342
343 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
344 #define CONFIG_PHY1_ADDR        2
345
346 /* Debug messages for the DDR autocalibration */
347 #define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
348
349 /*
350  * Default environment variables
351  */
352 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
353         CONFIG_AMCC_DEF_ENV                                             \
354         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
355         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
356         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
357         "logversion=2\0"                                                \
358         "kernel_addr=fc000000\0"                                        \
359         "fdt_addr=fc1e0000\0"                                           \
360         "ramdisk_addr=fc200000\0"                                       \
361         "pciconfighost=1\0"                                             \
362         "pcie_mode=RP:RP\0"                                             \
363         ""
364
365 /*
366  * Commands additional to the ones defined in amcc-common.h
367  */
368 #define CONFIG_CMD_CHIP_CONFIG
369 #define CONFIG_CMD_DATE
370 #define CONFIG_CMD_NAND
371 #define CONFIG_CMD_PCI
372 #define CONFIG_CMD_SNTP
373
374 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
375
376 /* POST support */
377 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
378                                  CONFIG_SYS_POST_CPU            | \
379                                  CONFIG_SYS_POST_ETHER          | \
380                                  CONFIG_SYS_POST_I2C            | \
381                                  CONFIG_SYS_POST_MEMORY_ON      | \
382                                  CONFIG_SYS_POST_UART)
383
384 /* Define here the base-addresses of the UARTs to test in POST */
385 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
386                         CONFIG_SYS_NS16550_COM2 }
387
388 #define CONFIG_LOGBUFFER
389 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
390
391 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
392
393 /*-----------------------------------------------------------------------
394  * PCI stuff
395  *----------------------------------------------------------------------*/
396 #define CONFIG_PCI                      /* include pci support          */
397 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
398 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
399 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
400 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
401
402 /*-----------------------------------------------------------------------
403  * PCIe stuff
404  *----------------------------------------------------------------------*/
405 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
406 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
407
408 #define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
409 #define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
410 #define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
411
412 #define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
413 #define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
414 #define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
415
416 #define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
417 #define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
418
419 /* base address of inbound PCIe window */
420 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
421
422 /*-----------------------------------------------------------------------
423  * External Bus Controller (EBC) Setup
424  *----------------------------------------------------------------------*/
425 #define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
426
427 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
428 #define CONFIG_SYS_EBC_PB0AP            0x05806500
429 #define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
430
431 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
432 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
433 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
434
435 /* Memory Bank 2 (FPGA) initialization                                  */
436 #define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
437                                          EBC_BXAP_FWT_ENCODE(6) |       \
438                                          EBC_BXAP_BWT_ENCODE(1) |       \
439                                          EBC_BXAP_BCE_DISABLE |         \
440                                          EBC_BXAP_BCT_2TRANS |          \
441                                          EBC_BXAP_CSN_ENCODE(0) |       \
442                                          EBC_BXAP_OEN_ENCODE(0) |       \
443                                          EBC_BXAP_WBN_ENCODE(3) |       \
444                                          EBC_BXAP_WBF_ENCODE(1) |       \
445                                          EBC_BXAP_TH_ENCODE(4) |        \
446                                          EBC_BXAP_RE_DISABLED |         \
447                                          EBC_BXAP_SOR_DELAYED |         \
448                                          EBC_BXAP_BEM_WRITEONLY |       \
449                                          EBC_BXAP_PEN_DISABLED)
450 #define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
451
452 #define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
453
454 /*-----------------------------------------------------------------------
455  * GPIO Setup
456  *----------------------------------------------------------------------*/
457 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
458 {                                                                                       \
459 /* GPIO Core 0 */                                                                       \
460 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
461 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
462 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
463 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
464 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
465 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
466 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
467 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
468 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
469 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
470 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
471 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
472 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
473 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
474 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
475 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
476 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
477 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
478 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
479 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
480 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
481 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
482 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
483 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
484 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
485 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
486 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
487 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
488 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
489 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
490 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
491 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
492 }                                                                                               \
493 }
494
495 /*-----------------------------------------------------------------------
496  * Some Kilauea stuff..., mainly fpga registers
497  */
498 #define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
499 #define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
500
501 /* interrupt */
502 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
503 #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
504 #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
505 #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
506 #define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
507 #define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
508 #define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
509 #define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
510
511 /* DPRAM setting */
512 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
513 #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
514 #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
515 #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
516 #define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
517 #define CONFIG_SYS_FPGA_UART0_FO                0x00020000
518 #define CONFIG_SYS_FPGA_UART1_FO                0x00010000
519
520 /* loopback */
521 #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
522 #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
523 #define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
524 #define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
525 #define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
526 #define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
527 #define CONFIG_SYS_FPGA_USER_LED0               0x00000200
528 #define CONFIG_SYS_FPGA_USER_LED1               0x00000100
529
530 #define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
531 #define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
532 #define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
533
534 #endif  /* __CONFIG_H */