git.sur5r.net Git - u-boot/blob - include/configs/km/km82xx-common.h

   1 /*
   2  * (C) Copyright 2007-2010
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __KM82XX_COMMON
  25 #define __KM82XX_COMMON
  26
  27 /*
  28  * Select serial console configuration
  29  *
  30  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  31  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  32  * for SCC).
  33  */
  34 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  35 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  36 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  37 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  38 #define CONFIG_SYS_SMC_RXBUFLEN 128
  39 #define CONFIG_SYS_MAXIDLE      10
  40
  41 /*
  42  * Select ethernet configuration
  43  *
  44  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  45  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  46  * SCC, 1-3 for FCC)
  47  *
  48  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  49  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  50  * must be unset.
  51  */
  52 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
  53 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
  54 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  55 #define CONFIG_NET_MULTI
  56
  57 #define CONFIG_ETHER_INDEX      4
  58 #define CONFIG_HAS_ETH0
  59 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
  60
  61 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
  62
  63 #ifndef CONFIG_8260_CLKIN
  64 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
  65 #endif
  66
  67 #define BOOTFLASH_START         0xFE000000
  68
  69 #define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
  70
  71 #define MTDPARTS_DEFAULT        "mtdparts="                             \
  72         "app:"                                                          \
  73                 "768k(u-boot),"                                         \
  74                 "128k(env),"                                            \
  75                 "128k(envred),"                                         \
  76                 "3072k(free),"                                          \
  77                 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  78
  79 /*
  80  * Default environment settings
  81  */
  82 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  83         CONFIG_KM_BOARD_EXTRA_ENV                                       \
  84         CONFIG_KM_DEF_ENV                                               \
  85         "EEprom_ivm=pca9544a:70:4 \0"                                   \
  86         "unlock=yes\0"                                                  \
  87         "newenv="                                                       \
  88                 "prot off 0xFE0C0000 +0x40000 && "                      \
  89                 "era 0xFE0C0000 +0x40000\0"                             \
  90         "arch=ppc_82xx\0"                                       \
  91         ""
  92
  93 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  94 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  95 #define CONFIG_SYS_RAMBOOT
  96 #endif
  97
  98 #define CONFIG_SYS_MONITOR_LEN          (768 << 10)
  99
 100 #define CONFIG_ENV_IS_IN_FLASH
 101
 102 #ifdef CONFIG_ENV_IS_IN_FLASH
 103 #define CONFIG_ENV_SECT_SIZE    0x20000
 104 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 105                                         CONFIG_SYS_MONITOR_LEN)
 106 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 107
 108 /* Address and size of Redundant Environment Sector     */
 109 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 110                                                 CONFIG_ENV_SECT_SIZE)
 111 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 112 #endif /* CONFIG_ENV_IS_IN_FLASH */
 113
 114 /* enable I2C and select the hardware/software driver */
 115 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 116 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 117 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed */
 118 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* I2C slave address */
 119
 120 /*
 121  * Software (bit-bang) I2C driver configuration
 122  */
 123
 124 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 125 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 126 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 127 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 128 #define I2C_SDA(bit)    do { \
 129                                 if (bit) \
 130                                         iop->pdat |=  0x00010000; \
 131                                 else \
 132                                         iop->pdat &= ~0x00010000; \
 133                         } while (0)
 134 #define I2C_SCL(bit)    do { \
 135                                 if (bit) \
 136                                         iop->pdat |=  0x00020000; \
 137                                 else \
 138                                         iop->pdat &= ~0x00020000; \
 139                         } while (0)
 140 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 141
 142 #ifndef __ASSEMBLY__
 143 void set_sda(int state);
 144 void set_scl(int state);
 145 int get_sda(void);
 146 int get_scl(void);
 147 #endif
 148
 149 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 150 #define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 151 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 152 #define CONFIG_SYS_DTT_MAX_TEMP 70
 153 #define CONFIG_SYS_DTT_LOW_TEMP -30
 154 #define CONFIG_SYS_DTT_HYSTERESIS       3
 155 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 156
 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 158
 159 #define CONFIG_SYS_IMMR         0xF0000000
 160
 161 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 162 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 163 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 164                                                 GENERATED_GBL_DATA_SIZE)
 165 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 166
 167 /* Hard reset configuration word */
 168 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 169
 170 /* No slaves */
 171 #define CONFIG_SYS_HRCW_SLAVE1          0
 172 #define CONFIG_SYS_HRCW_SLAVE2          0
 173 #define CONFIG_SYS_HRCW_SLAVE3          0
 174 #define CONFIG_SYS_HRCW_SLAVE4          0
 175 #define CONFIG_SYS_HRCW_SLAVE5          0
 176 #define CONFIG_SYS_HRCW_SLAVE6          0
 177 #define CONFIG_SYS_HRCW_SLAVE7          0
 178
 179 /* Initial Memory map for Linux */
 180 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 181
 182 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 183 #if defined(CONFIG_CMD_KGDB)
 184 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 185 #endif
 186
 187 #define CONFIG_SYS_HID0_INIT            0
 188 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 189
 190 #define CONFIG_SYS_HID2         0
 191
 192 #define CONFIG_SYS_SIUMCR               0x4020c200
 193 #define CONFIG_SYS_SYPCR                0xFFFFFF83
 194 #define CONFIG_SYS_BCR                  0x10000000
 195 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 196
 197 /*
 198  *-----------------------------------------------------------------------
 199  * RMR - Reset Mode Register                                     5-5
 200  *-----------------------------------------------------------------------
 201  * turn on Checkstop Reset Enable
 202  */
 203 #define CONFIG_SYS_RMR         0
 204
 205 /*
 206  *-----------------------------------------------------------------------
 207  * TMCNTSC - Time Counter Status and Control                     4-40
 208  *-----------------------------------------------------------------------
 209  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 210  * and enable Time Counter
 211  */
 212 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 213
 214 /*
 215  *-----------------------------------------------------------------------
 216  * PISCR - Periodic Interrupt Status and Control                 4-42
 217  *-----------------------------------------------------------------------
 218  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 219  * Periodic timer
 220  */
 221 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 222
 223 /*
 224  *-----------------------------------------------------------------------
 225  * RCCR - RISC Controller Configuration                         13-7
 226  *-----------------------------------------------------------------------
 227  */
 228 #define CONFIG_SYS_RCCR        0
 229
 230 /*
 231  * Init Memory Controller:
 232  *
 233  * Bank Bus     Machine PortSz  Device
 234  * ---- ---     ------- ------  ------
 235  *  0   60x     GPCM     8 bit  FLASH
 236  *  1   60x     SDRAM   32 bit  SDRAM
 237  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 238  *  5   60x     GPCM    16 bit  CFG-Flash
 239  *
 240  */
 241 /* Bank 0 - FLASH
 242  */
 243 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 244                          BRx_PS_8                       |\
 245                          BRx_MS_GPCM_P                  |\
 246                          BRx_V)
 247
 248 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 249                          ORxG_CSNT                      |\
 250                          ORxG_ACS_DIV2                  |\
 251                          ORxG_SCY_5_CLK                 |\
 252                          ORxG_TRLX)
 253
 254 #define CONFIG_SYS_MPTPR       0x1800
 255
 256 /*
 257  *-----------------------------------------------------------------------------
 258  * Address for Mode Register Set (MRS) command
 259  *-----------------------------------------------------------------------------
 260  */
 261 #define CONFIG_SYS_MRS_OFFS     0x00000110
 262 #define CONFIG_SYS_PSRT        0x0e
 263
 264 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 265                          BRx_PS_64              |\
 266                          BRx_MS_SDRAM_P         |\
 267                          BRx_V)
 268
 269 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 270
 271 /*
 272  * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 273  */
 274 #define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 275 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 276
 277 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 278                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 279
 280 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 281                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 282                          ORxG_SCY_3_CLK | ORxG_TRLX)
 283
 284 /*
 285  * BFTICU board FPGA on CS4 initialization values
 286  */
 287 #define CONFIG_SYS_FPGA_BASE    0x40000000
 288 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 289
 290 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 291                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 292
 293 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 294                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 295                          ORxG_SCY_3_CLK | ORxG_TRLX)
 296
 297 /*
 298  * CFG-Flash on CS5 initialization values
 299  */
 300 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 301                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 302
 303 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 304                                  CONFIG_SYS_FLASH_SIZE_2) |\
 305                                  ORxG_CSNT | ORxG_ACS_DIV2 |\
 306                                  ORxG_SCY_5_CLK | ORxG_TRLX)
 307
 308 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 309
 310 /* pass open firmware flat tree */
 311 #define CONFIG_FIT              1
 312 #define CONFIG_OF_LIBFDT        1
 313 #define CONFIG_OF_BOARD_SETUP   1
 314
 315 #define OF_TBCLK                (bd->bi_busfreq / 4)
 316 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 317
 318 #endif /* __KM82XX_COMMON */