3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __CONFIG_KM83XX_H
9 #define __CONFIG_KM83XX_H
11 #define CONFIG_DISPLAY_BOARDINFO
13 /* include common defines/options for all Keymile boards */
14 #include "keymile-common.h"
15 #include "km-powerpc.h"
17 #ifndef MTDIDS_DEFAULT
18 # define MTDIDS_DEFAULT "nor0=boot"
19 #endif /* MTDIDS_DEFAULT */
21 #ifndef MTDPARTS_DEFAULT
22 # define MTDPARTS_DEFAULT "mtdparts=" \
27 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
28 #endif /* MTDPARTS_DEFAULT */
30 #define CONFIG_MISC_INIT_R
34 #define CONFIG_83XX_CLKIN 66000000
35 #define CONFIG_SYS_CLK_FREQ 66000000
36 #define CONFIG_83XX_PCICLK 66000000
41 #define CONFIG_SYS_IMMR 0xE0000000
44 * Bus Arbitration Configuration Register (ACR)
46 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
47 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
48 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
49 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
56 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
58 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
59 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
60 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
62 #define CFG_83XX_DDR_USES_CS0
65 * Manually set up DDR parameters
68 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
74 #define CONFIG_SYS_FLASH_BASE 0xF0000000
76 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
77 #define CONFIG_SYS_RAMBOOT
80 /* Reserve 768 kB for Mon */
81 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
84 * Initial RAM Base Address Setup
86 #define CONFIG_SYS_INIT_RAM_LOCK
87 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
88 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
89 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
90 GENERATED_GBL_DATA_SIZE)
93 * Init Local Bus Memory Controller:
95 * Bank Bus Machine PortSz Size Device
96 * ---- --- ------- ------ ----- ------
97 * 0 Local GPCM 16 bit 256MB FLASH
98 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
102 * FLASH on the Local Bus
104 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
105 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
106 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
107 #define CONFIG_SYS_FLASH_PROTECTION
108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
110 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
111 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
113 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
114 BR_PS_16 | /* 16 bit port size */ \
115 BR_MS_GPCM | /* MSEL = GPCM */ \
118 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
119 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
121 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
123 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
124 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
125 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
128 * PRIO1/PIGGY on the local bus CS1
130 /* Window base at flash base */
131 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
132 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
134 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
135 BR_PS_8 | /* 8 bit port size */ \
136 BR_MS_GPCM | /* MSEL = GPCM */ \
138 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
139 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
141 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
146 #define CONFIG_CONS_INDEX 1
147 #define CONFIG_SYS_NS16550_SERIAL
148 #define CONFIG_SYS_NS16550_REG_SIZE 1
149 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
155 * QE UEC ethernet configuration
157 #define CONFIG_UEC_ETH
158 #define CONFIG_ETHPRIME "UEC0"
160 #if !defined(CONFIG_MPC8309)
161 #define CONFIG_UEC_ETH1 /* GETH1 */
162 #define UEC_VERBOSE_DEBUG 1
165 #ifdef CONFIG_UEC_ETH1
166 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
167 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
168 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
169 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
170 #define CONFIG_SYS_UEC1_PHY_ADDR 0
171 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
172 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
179 #ifndef CONFIG_SYS_RAMBOOT
180 #define CONFIG_ENV_IS_IN_FLASH
181 #ifndef CONFIG_ENV_ADDR
182 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
183 CONFIG_SYS_MONITOR_LEN)
185 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
186 #ifndef CONFIG_ENV_OFFSET
187 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
190 /* Address and size of Redundant Environment Sector */
191 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
192 CONFIG_ENV_SECT_SIZE)
193 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
195 #else /* CFG_SYS_RAMBOOT */
196 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
197 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
198 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
199 #define CONFIG_ENV_SIZE 0x2000
200 #endif /* CFG_SYS_RAMBOOT */
203 #define CONFIG_SYS_I2C
204 #define CONFIG_SYS_NUM_I2C_BUSES 4
205 #define CONFIG_SYS_I2C_MAX_HOPS 1
206 #define CONFIG_SYS_I2C_FSL
207 #define CONFIG_SYS_FSL_I2C_SPEED 200000
208 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
209 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
210 #define CONFIG_SYS_I2C_OFFSET 0x3000
211 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
212 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
213 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
214 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
215 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
216 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
217 {1, {I2C_NULL_HOP} } }
219 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
221 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
222 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */
223 #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
224 #define CONFIG_SYS_DTT_MAX_TEMP 70
225 #define CONFIG_SYS_DTT_HYSTERESIS 3
226 #define CONFIG_SYS_DTT_BUS_NUM 1
228 #if defined(CONFIG_CMD_NAND)
229 #define CONFIG_NAND_KMETER1
230 #define CONFIG_SYS_MAX_NAND_DEVICE 1
231 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
234 #if defined(CONFIG_PCI)
235 #define CONFIG_CMD_PCI
239 * For booting Linux, the board info and command line data
240 * have to be in the first 8 MB of memory, since this is
241 * the maximum mapped by the Linux kernel during initialization.
243 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
248 #define CONFIG_SYS_HID0_INIT 0x000000000
249 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
250 HID0_ENABLE_INSTRUCTION_CACHE)
251 #define CONFIG_SYS_HID2 HID2_HBE
257 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
259 /* DDR: cache cacheable */
260 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
261 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
262 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
264 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
265 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
267 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
268 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
269 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
270 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
272 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
273 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
275 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
276 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
278 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
280 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
281 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
282 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
284 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
285 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
287 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
289 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
290 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
291 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
293 /* Stack in dcache: cacheable, no memory coherence */
294 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
295 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
297 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
298 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
301 * Internal Definitions
303 #define BOOTFLASH_START 0xF0000000
305 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
308 * Environment Configuration
310 #define CONFIG_ENV_OVERWRITE
311 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
312 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
315 #ifndef CONFIG_KM_DEF_ARCH
316 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
319 #define CONFIG_EXTRA_ENV_SETTINGS \
323 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
324 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
328 #if defined(CONFIG_UEC_ETH)
329 #define CONFIG_HAS_ETH0
332 #endif /* __CONFIG_KM83XX_H */