2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
24 * High Level Configuration Options
26 #define CONFIG_E300 1 /* E300 family */
27 #define CONFIG_QE 1 /* Has QE */
28 #define CONFIG_MPC83XX 1 /* MPC83XX family */
29 #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
30 #define CONFIG_KMETER1 1 /* KMETER1 board specific */
32 /* include common defines/options for all Keymile boards */
33 #include "keymile-common.h"
35 #define CONFIG_MISC_INIT_R 1
39 #define CONFIG_83XX_CLKIN 66000000
40 #define CONFIG_SYS_CLK_FREQ 66000000
41 #define CONFIG_83XX_PCICLK 66000000
44 * Hardware Reset Configuration Word
46 #define CONFIG_SYS_HRCW_LOW (\
47 HRCWL_CSB_TO_CLKIN_4X1 | \
48 HRCWL_CORE_TO_CSB_2X1 | \
49 HRCWL_CE_PLL_VCO_DIV_2 | \
52 #define CONFIG_SYS_HRCW_HIGH (\
54 HRCWH_FROM_0X00000100 | \
55 HRCWH_BOOTSEQ_NORMAL | \
56 HRCWH_SW_WATCHDOG_DISABLE | \
57 HRCWH_ROM_LOC_LOCAL_16BIT | \
64 #define CONFIG_SYS_SICRH 0x00000006
65 #define CONFIG_SYS_SICRL 0x00000000
70 #define CONFIG_SYS_IMMR 0xE0000000
75 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
76 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
77 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
78 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
79 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
81 #define CFG_83XX_DDR_USES_CS0
86 * DDRCDR - DDR Control Driver Register
89 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
92 * Manually set up DDR parameters
95 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
97 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
98 CSCONFIG_ROW_BIT_13 | \
99 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
101 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
103 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
104 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
105 #define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
106 (0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
108 #define CONFIG_SYS_DDR_MODE 0x04440242
109 #define CONFIG_SYS_DDR_MODE2 0x00800000
111 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
112 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
113 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
114 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
115 (0 << TIMING_CFG0_WWT_SHIFT) | \
116 (0 << TIMING_CFG0_RRT_SHIFT) | \
117 (0 << TIMING_CFG0_WRT_SHIFT) | \
118 (0 << TIMING_CFG0_RWT_SHIFT))
120 #define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \
121 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
122 ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
123 ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
124 ( 2 << TIMING_CFG1_REFREC_SHIFT) | \
125 ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
126 ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
127 ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
129 #define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
130 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
131 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
132 (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
133 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
134 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
135 (4 << TIMING_CFG2_CPO_SHIFT))
137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
140 * The reserved memory
142 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
143 #define CONFIG_SYS_FLASH_BASE 0xF0000000
144 #define CONFIG_SYS_FLASH_BASE_1 0xF2000000
145 #define CONFIG_SYS_PIGGY_BASE 0x80000000
146 #define CONFIG_SYS_PAXE_BASE 0xA0000000
147 #define CONFIG_SYS_PAXE_SIZE 256
149 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
150 #define CONFIG_SYS_RAMBOOT
152 #undef CONFIG_SYS_RAMBOOT
155 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
156 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
159 * Initial RAM Base Address Setup
161 #define CONFIG_SYS_INIT_RAM_LOCK 1
162 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
163 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
164 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
165 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
168 * Local Bus Configuration & Clock Setup
170 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
173 * Init Local Bus Memory Controller:
175 * Bank Bus Machine PortSz Size Device
176 * ---- --- ------- ------ ----- ------
177 * 0 Local GPCM 16 bit 256MB FLASH
178 * 1 Local GPCM 8 bit 256KB GPIO/PIGGY
179 * 3 Local GPCM 8 bit 256MB PAXE
183 * FLASH on the Local Bus
185 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
186 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
187 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
188 #define CONFIG_SYS_FLASH_PROTECTION 1
189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
191 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
192 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
194 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
195 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
198 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
199 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
201 OR_GPCM_TRLX | OR_GPCM_EAD)
203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
205 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
207 #undef CONFIG_SYS_FLASH_CHECKSUM
210 * PRIO1/PIGGY on the local bus CS1
212 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
213 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */
215 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
216 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
218 #define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \
219 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
221 OR_GPCM_TRLX | OR_GPCM_EAD)
224 * PAXE on the local bus CS3
226 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
227 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */
229 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
230 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
232 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
233 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
235 OR_GPCM_TRLX | OR_GPCM_EAD)
240 #define CONFIG_CONS_INDEX 1
241 #undef CONFIG_SERIAL_SOFTWARE_FIFO
242 #define CONFIG_SYS_NS16550
243 #define CONFIG_SYS_NS16550_SERIAL
244 #define CONFIG_SYS_NS16550_REG_SIZE 1
245 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
247 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
248 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
250 /* Pass open firmware flat tree */
251 #define CONFIG_OF_LIBFDT 1
252 #define CONFIG_OF_BOARD_SETUP 1
253 #define CONFIG_OF_STDOUT_VIA_ALIAS
257 * Addresses are mapped 1-1.
259 #undef CONFIG_PCI /* No PCI */
261 #ifndef CONFIG_NET_MULTI
262 #define CONFIG_NET_MULTI 1
265 * QE UEC ethernet configuration
267 #define CONFIG_UEC_ETH
268 #define CONFIG_ETHPRIME "FSL UEC0"
270 #define CONFIG_UEC_ETH1 /* GETH1 */
271 #define UEC_VERBOSE_DEBUG 1
273 #ifdef CONFIG_UEC_ETH1
274 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
275 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
276 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
277 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
278 #define CONFIG_SYS_UEC1_PHY_ADDR 0
279 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
286 #ifndef CONFIG_SYS_RAMBOOT
287 #define CONFIG_ENV_IS_IN_FLASH 1
288 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
289 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
290 #define CONFIG_ENV_SIZE 0x20000
291 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
293 /* Address and size of Redundant Environment Sector */
294 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
295 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
297 #else /* CFG_RAMBOOT */
298 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
299 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
300 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
301 #define CONFIG_ENV_SIZE 0x2000
302 #endif /* CFG_RAMBOOT */
305 #define CONFIG_HARD_I2C /* I2C with hardware support */
306 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
307 #define CONFIG_FSL_I2C
308 #define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
309 #define CONFIG_SYS_I2C_SLAVE 0x7F
310 #define CONFIG_SYS_I2C_OFFSET 0x3000
311 #define CONFIG_I2C_MULTI_BUS 1
312 #define CONFIG_I2C_CMD_TREE 1
313 #define CONFIG_SYS_MAX_I2C_BUS 2
314 #define CONFIG_I2C_MUX 1
317 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
318 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
320 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
321 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
323 /* Support the IVM EEprom */
324 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50
325 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
326 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
328 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
329 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
330 #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
331 #define CONFIG_SYS_DTT_MAX_TEMP 70
332 #define CONFIG_SYS_DTT_LOW_TEMP -30
333 #define CONFIG_SYS_DTT_HYSTERESIS 3
334 #define CONFIG_SYS_DTT_BUS_NUM (2)
336 #if defined(CONFIG_PCI)
337 #define CONFIG_CMD_PCI
340 #if defined(CFG_RAMBOOT)
341 #undef CONFIG_CMD_SAVEENV
342 #undef CONFIG_CMD_LOADS
346 * For booting Linux, the board info and command line data
347 * have to be in the first 8 MB of memory, since this is
348 * the maximum mapped by the Linux kernel during initialization.
350 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
355 #define CONFIG_SYS_HID0_INIT 0x000000000
356 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
357 #define CONFIG_SYS_HID2 HID2_HBE
363 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
365 /* DDR: cache cacheable */
366 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
367 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
368 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
369 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
370 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
372 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
373 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
374 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
375 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
376 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
377 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
379 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
380 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
381 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
382 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
383 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
384 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
386 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
387 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
388 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
389 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
390 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
391 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
393 /* Stack in dcache: cacheable, no memory coherence */
394 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
395 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
396 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
397 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
399 /* PAXE: icache cacheable, but dcache-inhibit and guarded */
400 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
401 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
402 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
403 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
404 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
407 /* PCI MEM space: cacheable */
408 #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
409 #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
410 #define CFG_DBAT6L CFG_IBAT6L
411 #define CFG_DBAT6U CFG_IBAT6U
412 /* PCI MMIO space: cache-inhibit and guarded */
413 #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
414 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
415 #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
416 #define CFG_DBAT7L CFG_IBAT7L
417 #define CFG_DBAT7U CFG_IBAT7U
418 #else /* CONFIG_PCI */
419 #define CONFIG_SYS_IBAT6L (0)
420 #define CONFIG_SYS_IBAT6U (0)
421 #define CONFIG_SYS_IBAT7L (0)
422 #define CONFIG_SYS_IBAT7U (0)
423 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
424 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
425 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
426 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
427 #endif /* CONFIG_PCI */
430 * Internal Definitions
434 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
435 #define BOOTFLAG_WARM 0x02 /* Software reboot */
438 * Environment Configuration
440 #define CONFIG_ENV_OVERWRITE
442 #if defined(CONFIG_UEC_ETH)
443 #define CONFIG_HAS_ETH0
446 #define CONFIG_EXTRA_ENV_SETTINGS \
448 "rootpath=/opt/eldk/ppc_82xx\0" \
449 "nfsargs=setenv bootargs root=/dev/nfs rw " \
450 "nfsroot=${serverip}:${rootpath}\0" \
451 "ramargs=setenv bootargs root=/dev/ram rw\0" \
452 "addip=setenv bootargs ${bootargs} " \
453 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
454 ":${hostname}:${netdev}:off panic=1\0" \
455 "addtty=setenv bootargs ${bootargs}" \
456 " console=ttyS0,${baudrate}\0" \
457 "fdt_addr=f0080000\0" \
458 "kernel_addr=f00a0000\0" \
459 "ramdisk_addr=f03a0000\0" \
460 "kernel_addr_r=400000\0" \
461 "fdt_addr_r=800000\0" \
462 "ramdisk_addr_r=810000\0" \
463 "flash_self=run ramargs addip addtty;" \
464 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
465 "flash_nfs=run nfsargs addip addtty;" \
466 "bootm ${kernel_addr} - ${fdt_addr}\0" \
467 "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \
468 "tftp ${fdt_addr_r} ${fdt_file}; " \
469 "run nfsargs addip addtty;" \
470 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
471 "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \
472 "boot_file=/tftpboot/kmeter1/uImage\0" \
473 "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
474 "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \
475 "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
476 "load=tftp $loadaddr ${u-boot}\0" \
477 "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \
478 "erase " MK_STR(TEXT_BASE) " +$filesize;" \
479 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
480 "protect on " MK_STR(TEXT_BASE) " +$filesize;" \
481 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
482 "setenv filesize;saveenv\0" \
483 "upd=run load update\0" \
484 "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
485 "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
486 "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \
488 "EEprom_ivm=pca9547:70:9\0" \
489 "dtt_bus=pca9547:70:a\0" \
492 #endif /* __CONFIG_H */