2 * Common configuration header file for all Keystone II EVM platforms
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __CONFIG_KS2_EVM_H
11 #define __CONFIG_KS2_EVM_H
13 #define CONFIG_SOC_KEYSTONE
15 /* U-Boot Build Configuration */
16 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
17 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
18 #define CONFIG_SYS_CONSOLE_INFO_QUIET
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_SYS_THUMB_BUILD
22 /* SoC Configuration */
24 #define CONFIG_ARCH_CPU_INIT
25 #define CONFIG_SYS_ARCH_TIMER
26 #define CONFIG_SYS_HZ 1000
27 #define CONFIG_SYS_TEXT_BASE 0x0c001000
28 #define CONFIG_SPL_TARGET "u-boot-spi.gph"
29 #define CONFIG_SYS_DCACHE_OFF
31 /* Memory Configuration */
32 #define CONFIG_NR_DRAM_BANKS 2
33 #define CONFIG_SYS_SDRAM_BASE 0x80000000
34 #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
35 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
36 #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
37 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
39 GENERATED_GBL_DATA_SIZE)
41 /* SPL SPI Loader Configuration */
42 #define CONFIG_SPL_PAD_TO 65536
43 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
44 #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
46 #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
47 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
48 CONFIG_SPL_BSS_MAX_SIZE)
49 #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
50 #define CONFIG_SPL_STACK_SIZE (8 * 1024)
51 #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
52 CONFIG_SYS_SPL_MALLOC_SIZE + \
53 CONFIG_SPL_STACK_SIZE - 4)
54 #define CONFIG_SPL_LIBCOMMON_SUPPORT
55 #define CONFIG_SPL_LIBGENERIC_SUPPORT
56 #define CONFIG_SPL_SERIAL_SUPPORT
57 #define CONFIG_SPL_SPI_FLASH_SUPPORT
58 #define CONFIG_SPL_SPI_SUPPORT
59 #define CONFIG_SPL_BOARD_INIT
60 #define CONFIG_SPL_SPI_LOAD
61 #define CONFIG_SPL_SPI_BUS 0
62 #define CONFIG_SPL_SPI_CS 0
63 #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
64 #define CONFIG_SPL_FRAMEWORK
66 /* UART Configuration */
67 #define CONFIG_SYS_NS16550
68 #define CONFIG_SYS_NS16550_SERIAL
69 #define CONFIG_SYS_NS16550_MEM32
70 #define CONFIG_SYS_NS16550_REG_SIZE -4
71 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
72 #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
73 #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
74 #define CONFIG_CONS_INDEX 1
75 #define CONFIG_BAUDRATE 115200
77 /* SPI Configuration */
79 #define CONFIG_SPI_FLASH
80 #define CONFIG_SPI_FLASH_STMICRO
81 #define CONFIG_DAVINCI_SPI
82 #define CONFIG_CMD_SPI
83 #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
84 #define CONFIG_SF_DEFAULT_SPEED 30000000
85 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
86 #define CONFIG_SYS_SPI0
87 #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
88 #define CONFIG_SYS_SPI0_NUM_CS 4
89 #define CONFIG_SYS_SPI1
90 #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
91 #define CONFIG_SYS_SPI1_NUM_CS 4
92 #define CONFIG_SYS_SPI2
93 #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
94 #define CONFIG_SYS_SPI2_NUM_CS 4
96 /* Network Configuration */
98 #define CONFIG_BOOTP_DEFAULT
99 #define CONFIG_BOOTP_DNS
100 #define CONFIG_BOOTP_DNS2
101 #define CONFIG_BOOTP_SEND_HOSTNAME
102 #define CONFIG_NET_RETRY_COUNT 32
103 #define CONFIG_NET_MULTI
104 #define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
105 #define CONFIG_SYS_SGMII_REFCLK_MHZ 312
106 #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
107 #define CONFIG_SYS_SGMII_RATESCALE 2
110 #define CONFIG_TI_AEMIF
111 #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
113 /* I2C Configuration */
114 #define CONFIG_SYS_I2C
115 #define CONFIG_SYS_I2C_DAVINCI
116 #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
117 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
118 #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
119 #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
120 #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
121 #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
122 #define I2C_BUS_MAX 3
124 /* EEPROM definitions */
125 #define CONFIG_SYS_I2C_MULTI_EEPROMS
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
127 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
129 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
130 #define CONFIG_ENV_EEPROM_IS_ON_I2C
132 /* NAND Configuration */
133 #define CONFIG_NAND_DAVINCI
134 #define CONFIG_KEYSTONE_RBL_NAND
135 #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
136 #define CONFIG_SYS_NAND_MASK_CLE 0x4000
137 #define CONFIG_SYS_NAND_MASK_ALE 0x2000
138 #define CONFIG_SYS_NAND_CS 2
139 #define CONFIG_SYS_NAND_USE_FLASH_BBT
140 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
142 #define CONFIG_SYS_NAND_LARGEPAGE
143 #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
144 #define CONFIG_SYS_MAX_NAND_DEVICE 1
145 #define CONFIG_SYS_NAND_MAX_CHIPS 1
146 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
147 #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
148 #define CONFIG_ENV_IS_IN_NAND
149 #define CONFIG_ENV_OFFSET 0x100000
150 #define CONFIG_MTD_PARTITIONS
151 #define CONFIG_MTD_DEVICE
152 #define CONFIG_RBTREE
154 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
155 #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
156 "1024k(bootloader)ro,512k(params)ro," \
159 /* U-Boot command configuration */
160 #include <config_cmd_default.h>
161 #define CONFIG_CMD_ASKENV
162 #define CONFIG_CMD_DHCP
163 #define CONFIG_CMD_I2C
164 #define CONFIG_CMD_PING
165 #define CONFIG_CMD_SAVES
166 #define CONFIG_CMD_MTDPARTS
167 #define CONFIG_CMD_NAND
168 #define CONFIG_CMD_UBI
169 #define CONFIG_CMD_UBIFS
170 #define CONFIG_CMD_SF
171 #define CONFIG_CMD_EEPROM
173 /* U-Boot general configuration */
174 #define CONFIG_SYS_GENERIC_BOARD
175 #define CONFIG_SYS_CBSIZE 1024
176 #define CONFIG_SYS_PBSIZE 2048
177 #define CONFIG_SYS_MAXARGS 16
178 #define CONFIG_SYS_HUSH_PARSER
179 #define CONFIG_SYS_LONGHELP
180 #define CONFIG_CRC32_VERIFY
181 #define CONFIG_MX_CYCLIC
182 #define CONFIG_CMDLINE_EDITING
183 #define CONFIG_VERSION_VARIABLE
184 #define CONFIG_TIMESTAMP
187 #define CONFIG_TI_EDMA3
189 #define CONFIG_BOOTDELAY 3
190 #define CONFIG_BOOTFILE "uImage"
191 #define CONFIG_EXTRA_ENV_SETTINGS \
194 "nfs_root=/export\0" \
196 "mem_reserve=512M\0" \
197 "addr_fdt=0x87000000\0" \
198 "addr_kern=0x88000000\0" \
200 "addr_uboot=0x87000000\0" \
201 "addr_fs=0x82000000\0" \
202 "addr_ubi=0x82000000\0" \
203 "addr_secdb_key=0xc000000\0" \
204 "fdt_high=0xffffffff\0" \
206 "name_fs=arago-console-image.cpio.gz\0" \
207 "name_kern=uImage\0" \
211 "run_mon=mon_install ${addr_mon}\0" \
212 "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
213 "init_net=run args_all args_net\0" \
214 "init_ubi=run args_all args_ubi; " \
215 "ubi part ubifs; ubifsmount boot;" \
216 "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
217 "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
218 "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
219 "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
220 "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
221 "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
222 "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
223 "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
224 "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
225 "sf write ${addr_uboot} 0 ${filesize}\0" \
226 "burn_uboot_nand=nand erase 0 0x100000; " \
227 "nand write ${addr_uboot} 0 ${filesize}\0" \
228 "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
230 "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
231 "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
232 "${nfs_options} ip=dhcp\0" \
233 "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
234 "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
235 "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
236 "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
237 "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
238 "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
239 "burn_ubi=nand erase.part ubifs; " \
240 "nand write ${addr_ubi} ubifs ${filesize}\0" \
241 "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
242 "args_ramfs=setenv bootargs ${bootargs} " \
243 "rdinit=/sbin/init rw root=/dev/ram0 " \
244 "initrd=0x802000000,9M\0" \
246 "mtdparts=mtdparts=davinci_nand.0:" \
247 "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
249 #define CONFIG_BOOTCOMMAND \
250 "run init_${boot} get_fdt_${boot} get_mon_${boot} " \
251 "get_kern_${boot} run_mon run_kern"
253 #define CONFIG_BOOTARGS \
255 /* Linux interfacing */
256 #define CONFIG_CMDLINE_TAG
257 #define CONFIG_SETUP_MEMORY_TAGS
258 #define CONFIG_OF_LIBFDT 1
259 #define CONFIG_OF_BOARD_SETUP
260 #define CONFIG_SYS_BARGSIZE 1024
261 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
262 #define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
264 #define CONFIG_SUPPORT_RAW_INITRD
266 /* we may include files below only after all above definitions */
267 #include <asm/arch/hardware.h>
268 #include <asm/arch/clock.h>
269 #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
271 /* Maximum memory size for relocated U-boot at the end of the DDR3 memory
272 which is NOT applicable for DDR ECC test */
273 #define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
275 #endif /* __CONFIG_KS2_EVM_H */