2 * Common configuration header file for all Keystone II EVM platforms
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __CONFIG_KS2_EVM_H
11 #define __CONFIG_KS2_EVM_H
13 #define CONFIG_SOC_KEYSTONE
15 /* U-Boot Build Configuration */
16 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
17 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
18 #define CONFIG_SYS_CONSOLE_INFO_QUIET
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_SYS_THUMB_BUILD
22 /* SoC Configuration */
24 #define CONFIG_ARCH_CPU_INIT
25 #define CONFIG_SYS_ARCH_TIMER
26 #define CONFIG_SYS_TEXT_BASE 0x0c001000
27 #define CONFIG_SPL_TARGET "u-boot-spi.gph"
28 #define CONFIG_SYS_DCACHE_OFF
30 /* Memory Configuration */
31 #define CONFIG_NR_DRAM_BANKS 2
32 #define CONFIG_SYS_SDRAM_BASE 0x80000000
33 #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
34 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
35 #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
36 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */
37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
38 GENERATED_GBL_DATA_SIZE)
40 /* SPL SPI Loader Configuration */
41 #define CONFIG_SPL_PAD_TO 65536
42 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
43 #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
45 #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
46 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
47 CONFIG_SPL_BSS_MAX_SIZE)
48 #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
49 #define CONFIG_SPL_STACK_SIZE (8 * 1024)
50 #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
51 CONFIG_SYS_SPL_MALLOC_SIZE + \
52 CONFIG_SPL_STACK_SIZE - 4)
53 #define CONFIG_SPL_LIBCOMMON_SUPPORT
54 #define CONFIG_SPL_LIBGENERIC_SUPPORT
55 #define CONFIG_SPL_SERIAL_SUPPORT
56 #define CONFIG_SPL_SPI_FLASH_SUPPORT
57 #define CONFIG_SPL_SPI_SUPPORT
58 #define CONFIG_SPL_BOARD_INIT
59 #define CONFIG_SPL_SPI_LOAD
60 #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
61 #define CONFIG_SPL_FRAMEWORK
63 /* UART Configuration */
64 #define CONFIG_SYS_NS16550
65 #define CONFIG_SYS_NS16550_SERIAL
66 #define CONFIG_SYS_NS16550_MEM32
67 #define CONFIG_SYS_NS16550_REG_SIZE -4
68 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
69 #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
70 #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
71 #define CONFIG_CONS_INDEX 1
72 #define CONFIG_BAUDRATE 115200
74 /* SPI Configuration */
76 #define CONFIG_SPI_FLASH
77 #define CONFIG_SPI_FLASH_STMICRO
78 #define CONFIG_DAVINCI_SPI
79 #define CONFIG_CMD_SPI
80 #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
81 #define CONFIG_SF_DEFAULT_SPEED 30000000
82 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
83 #define CONFIG_SYS_SPI0
84 #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
85 #define CONFIG_SYS_SPI0_NUM_CS 4
86 #define CONFIG_SYS_SPI1
87 #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
88 #define CONFIG_SYS_SPI1_NUM_CS 4
89 #define CONFIG_SYS_SPI2
90 #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
91 #define CONFIG_SYS_SPI2_NUM_CS 4
93 /* Network Configuration */
95 #define CONFIG_BOOTP_DEFAULT
96 #define CONFIG_BOOTP_DNS
97 #define CONFIG_BOOTP_DNS2
98 #define CONFIG_BOOTP_SEND_HOSTNAME
99 #define CONFIG_NET_RETRY_COUNT 32
100 #define CONFIG_NET_MULTI
101 #define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
102 #define CONFIG_SYS_SGMII_REFCLK_MHZ 312
103 #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
104 #define CONFIG_SYS_SGMII_RATESCALE 2
107 #define CONFIG_TI_AEMIF
108 #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
110 /* I2C Configuration */
111 #define CONFIG_SYS_I2C
112 #define CONFIG_SYS_I2C_DAVINCI
113 #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
114 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
115 #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
116 #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
117 #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
118 #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
119 #define I2C_BUS_MAX 3
121 /* EEPROM definitions */
122 #define CONFIG_SYS_I2C_MULTI_EEPROMS
123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
126 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
127 #define CONFIG_ENV_EEPROM_IS_ON_I2C
129 /* NAND Configuration */
130 #define CONFIG_NAND_DAVINCI
131 #define CONFIG_KEYSTONE_RBL_NAND
132 #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
133 #define CONFIG_SYS_NAND_MASK_CLE 0x4000
134 #define CONFIG_SYS_NAND_MASK_ALE 0x2000
135 #define CONFIG_SYS_NAND_CS 2
136 #define CONFIG_SYS_NAND_USE_FLASH_BBT
137 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
139 #define CONFIG_SYS_NAND_LARGEPAGE
140 #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
141 #define CONFIG_SYS_MAX_NAND_DEVICE 1
142 #define CONFIG_SYS_NAND_MAX_CHIPS 1
143 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
144 #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
145 #define CONFIG_ENV_IS_IN_NAND
146 #define CONFIG_ENV_OFFSET 0x100000
147 #define CONFIG_MTD_PARTITIONS
148 #define CONFIG_MTD_DEVICE
149 #define CONFIG_RBTREE
151 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
152 #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
153 "1024k(bootloader)ro,512k(params)ro," \
156 /* U-Boot command configuration */
157 #include <config_cmd_default.h>
158 #define CONFIG_CMD_ASKENV
159 #define CONFIG_CMD_DHCP
160 #define CONFIG_CMD_I2C
161 #define CONFIG_CMD_PING
162 #define CONFIG_CMD_SAVES
163 #define CONFIG_CMD_MTDPARTS
164 #define CONFIG_CMD_NAND
165 #define CONFIG_CMD_UBI
166 #define CONFIG_CMD_UBIFS
167 #define CONFIG_CMD_SF
168 #define CONFIG_CMD_EEPROM
170 /* U-Boot general configuration */
171 #define CONFIG_SYS_GENERIC_BOARD
172 #define CONFIG_SYS_CBSIZE 1024
173 #define CONFIG_SYS_PBSIZE 2048
174 #define CONFIG_SYS_MAXARGS 16
175 #define CONFIG_SYS_HUSH_PARSER
176 #define CONFIG_SYS_LONGHELP
177 #define CONFIG_CRC32_VERIFY
178 #define CONFIG_MX_CYCLIC
179 #define CONFIG_CMDLINE_EDITING
180 #define CONFIG_VERSION_VARIABLE
181 #define CONFIG_TIMESTAMP
184 #define CONFIG_TI_EDMA3
186 #define CONFIG_BOOTDELAY 3
187 #define CONFIG_BOOTFILE "uImage"
188 #define CONFIG_EXTRA_ENV_SETTINGS \
191 "nfs_root=/export\0" \
193 "mem_reserve=512M\0" \
194 "addr_fdt=0x87000000\0" \
195 "addr_kern=0x88000000\0" \
197 "addr_uboot=0x87000000\0" \
198 "addr_fs=0x82000000\0" \
199 "addr_ubi=0x82000000\0" \
200 "addr_secdb_key=0xc000000\0" \
201 "fdt_high=0xffffffff\0" \
203 "name_fs=arago-console-image.cpio.gz\0" \
204 "name_kern=uImage\0" \
208 "run_mon=mon_install ${addr_mon}\0" \
209 "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
210 "init_net=run args_all args_net\0" \
211 "init_ubi=run args_all args_ubi; " \
212 "ubi part ubifs; ubifsmount boot;" \
213 "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
214 "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
215 "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
216 "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
217 "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
218 "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
219 "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
220 "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
221 "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
222 "sf write ${addr_uboot} 0 ${filesize}\0" \
223 "burn_uboot_nand=nand erase 0 0x100000; " \
224 "nand write ${addr_uboot} 0 ${filesize}\0" \
225 "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
227 "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
228 "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
229 "${nfs_options} ip=dhcp\0" \
230 "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
231 "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
232 "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
233 "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
234 "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
235 "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
236 "burn_ubi=nand erase.part ubifs; " \
237 "nand write ${addr_ubi} ubifs ${filesize}\0" \
238 "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
239 "args_ramfs=setenv bootargs ${bootargs} " \
240 "rdinit=/sbin/init rw root=/dev/ram0 " \
241 "initrd=0x802000000,9M\0" \
243 "mtdparts=mtdparts=davinci_nand.0:" \
244 "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
246 #define CONFIG_BOOTCOMMAND \
247 "run init_${boot} get_fdt_${boot} get_mon_${boot} " \
248 "get_kern_${boot} run_mon run_kern"
250 #define CONFIG_BOOTARGS \
252 /* Linux interfacing */
253 #define CONFIG_CMDLINE_TAG
254 #define CONFIG_SETUP_MEMORY_TAGS
255 #define CONFIG_OF_LIBFDT 1
256 #define CONFIG_OF_BOARD_SETUP
257 #define CONFIG_SYS_BARGSIZE 1024
258 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
259 #define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
261 #define CONFIG_SUPPORT_RAW_INITRD
263 /* we may include files below only after all above definitions */
264 #include <asm/arch/hardware.h>
265 #include <asm/arch/clock.h>
266 #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
268 /* Maximum memory size for relocated U-boot at the end of the DDR3 memory
269 which is NOT applicable for DDR ECC test */
270 #define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
272 #endif /* __CONFIG_KS2_EVM_H */