3 * Sangmoon Kim, dogoil@etinsys.com.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_MPC824X 1
12 #define CONFIG_MPC8245 1
13 #define CONFIG_KVME080 1
15 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
17 #define CONFIG_CONS_INDEX 1
19 #define CONFIG_BAUDRATE 115200
21 #define CONFIG_BOOTDELAY 5
23 #define CONFIG_IPADDR 192.168.0.2
24 #define CONFIG_NETMASK 255.255.255.0
25 #define CONFIG_SERVERIP 192.168.0.1
27 #define CONFIG_BOOTARGS \
28 "console=ttyS0,115200 " \
29 "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
30 "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
31 "kvme080:eth0:none " \
32 "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
34 #define CONFIG_BOOTCOMMAND \
35 "tftp 800000 kvme080/uImage; " \
38 #define CONFIG_LOADADDR 800000
40 #define CONFIG_BOARD_EARLY_INIT_F
41 #define CONFIG_BOARD_EARLY_INIT_R
42 #define CONFIG_MISC_INIT_R
44 #define CONFIG_LOADS_ECHO 1
45 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
47 #undef CONFIG_WATCHDOG
52 #define CONFIG_BOOTP_SUBNETMASK
53 #define CONFIG_BOOTP_GATEWAY
54 #define CONFIG_BOOTP_HOSTNAME
55 #define CONFIG_BOOTP_BOOTPATH
56 #define CONFIG_BOOTP_BOOTFILESIZE
59 #define CONFIG_MAC_PARTITION
60 #define CONFIG_DOS_PARTITION
62 #define CONFIG_RTC_DS164x
66 * Command line configuration.
68 #include <config_cmd_default.h>
70 #define CONFIG_CMD_ASKENV
71 #define CONFIG_CMD_CACHE
72 #define CONFIG_CMD_DATE
73 #define CONFIG_CMD_DHCP
74 #define CONFIG_CMD_DIAG
75 #define CONFIG_CMD_EEPROM
76 #define CONFIG_CMD_ELF
77 #define CONFIG_CMD_I2C
78 #define CONFIG_CMD_JFFS2
79 #define CONFIG_CMD_NFS
80 #define CONFIG_CMD_PCI
81 #define CONFIG_CMD_PING
82 #define CONFIG_CMD_SDRAM
83 #define CONFIG_CMD_SNTP
86 #define CONFIG_NETCONSOLE
88 #define CONFIG_SYS_LONGHELP
89 #define CONFIG_SYS_CBSIZE 256
90 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
91 #define CONFIG_SYS_MAXARGS 16
92 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
94 #define CONFIG_SYS_MEMTEST_START 0x00400000
95 #define CONFIG_SYS_MEMTEST_END 0x07C00000
97 #define CONFIG_SYS_LOAD_ADDR 0x00100000
99 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
100 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
101 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_SDRAM_BASE 0x00000000
104 #define CONFIG_SYS_FLASH_BASE 0x7C000000
105 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
106 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000
107 #define CONFIG_SYS_NS16550_COM1 0xFF080000
108 #define CONFIG_SYS_NS16550_COM2 0xFF080010
109 #define CONFIG_SYS_NS16550_COM3 0xFF080020
110 #define CONFIG_SYS_NS16550_COM4 0xFF080030
111 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
113 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
114 #define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
115 #define CONFIG_SYS_NVRAM_SIZE 0x7FFF8
117 #define CONFIG_VERY_BIG_RAM
119 #define CONFIG_SYS_MONITOR_LEN 0x00040000
120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
121 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
123 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
125 #define CONFIG_SYS_FLASH_CFI
126 #define CONFIG_FLASH_CFI_DRIVER
127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
128 #define CONFIG_SYS_FLASH_PROTECTION
129 #define CONFIG_SYS_FLASH_EMPTY_INFO
130 #define CONFIG_SYS_FLASH_PROTECT_CLEAR
132 #define CONFIG_SYS_MAX_FLASH_BANKS 1
133 #define CONFIG_SYS_MAX_FLASH_SECT 256
135 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
136 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
138 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
139 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
141 #define CONFIG_ENV_IS_IN_NVRAM 1
142 #define CONFIG_ENV_OVERWRITE 1
143 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
144 #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
145 #define CONFIG_ENV_SIZE 0x400
146 #define CONFIG_ENV_OFFSET 0
148 #define CONFIG_SYS_NS16550
149 #define CONFIG_SYS_NS16550_SERIAL
150 #define CONFIG_SYS_NS16550_REG_SIZE 1
151 #define CONFIG_SYS_NS16550_CLK 14745600
154 #define CONFIG_PCI_INDIRECT_BRIDGE
155 #define CONFIG_PCI_PNP
157 #define CONFIG_EEPRO100
158 #define CONFIG_EEPRO100_SROM_WRITE
160 #define CONFIG_SYS_RX_ETH_BUFFER 8
162 #define CONFIG_HARD_I2C 1
163 #define CONFIG_SYS_I2C_SPEED 400000
164 #define CONFIG_SYS_I2C_SLAVE 0x7F
166 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
167 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
169 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
171 #define CONFIG_SYS_CLK_FREQ 33333333
173 #define CONFIG_SYS_CACHELINE_SIZE 32
174 #if defined(CONFIG_CMD_KGDB)
175 # define CONFIG_SYS_CACHELINE_SHIFT 5
178 #define CONFIG_SYS_DLL_EXTEND 0x00
179 #define CONFIG_SYS_PCI_HOLD_DEL 0x20
181 #define CONFIG_SYS_ROMNAL 15
182 #define CONFIG_SYS_ROMFAL 31
184 #define CONFIG_SYS_REFINT 430
186 #define CONFIG_SYS_DBUS_SIZE2 1
188 #define CONFIG_SYS_BSTOPRE 121
189 #define CONFIG_SYS_REFREC 8
190 #define CONFIG_SYS_RDLAT 4
191 #define CONFIG_SYS_PRETOACT 3
192 #define CONFIG_SYS_ACTTOPRE 5
193 #define CONFIG_SYS_ACTORW 3
194 #define CONFIG_SYS_SDMODE_CAS_LAT 3
195 #define CONFIG_SYS_SDMODE_WRAP 0
197 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
198 #define CONFIG_SYS_EXTROM 1
199 #define CONFIG_SYS_REGDIMM 0
201 #define CONFIG_SYS_BANK0_START 0x00000000
202 #define CONFIG_SYS_BANK0_END (0x4000000 - 1)
203 #define CONFIG_SYS_BANK0_ENABLE 1
204 #define CONFIG_SYS_BANK1_START 0x04000000
205 #define CONFIG_SYS_BANK1_END (0x8000000 - 1)
206 #define CONFIG_SYS_BANK1_ENABLE 1
207 #define CONFIG_SYS_BANK2_START 0x3ff00000
208 #define CONFIG_SYS_BANK2_END 0x3fffffff
209 #define CONFIG_SYS_BANK2_ENABLE 0
210 #define CONFIG_SYS_BANK3_START 0x3ff00000
211 #define CONFIG_SYS_BANK3_END 0x3fffffff
212 #define CONFIG_SYS_BANK3_ENABLE 0
213 #define CONFIG_SYS_BANK4_START 0x00000000
214 #define CONFIG_SYS_BANK4_END 0x00000000
215 #define CONFIG_SYS_BANK4_ENABLE 0
216 #define CONFIG_SYS_BANK5_START 0x00000000
217 #define CONFIG_SYS_BANK5_END 0x00000000
218 #define CONFIG_SYS_BANK5_ENABLE 0
219 #define CONFIG_SYS_BANK6_START 0x00000000
220 #define CONFIG_SYS_BANK6_END 0x00000000
221 #define CONFIG_SYS_BANK6_ENABLE 0
222 #define CONFIG_SYS_BANK7_START 0x00000000
223 #define CONFIG_SYS_BANK7_END 0x00000000
224 #define CONFIG_SYS_BANK7_ENABLE 0
226 #define CONFIG_SYS_BANK_ENABLE 0x03
228 #define CONFIG_SYS_ODCR 0x75
229 #define CONFIG_SYS_PGMAX 0x32
231 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
232 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
234 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
235 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
237 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
238 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
240 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
241 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
243 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
244 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
245 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
246 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
247 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
248 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
249 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
250 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
252 #endif /* __CONFIG_H */