3 * Sangmoon Kim, dogoil@etinsys.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define CONFIG_MPC824X 1
28 #define CONFIG_MPC8245 1
29 #define CONFIG_KVME080 1
31 #define CONFIG_CONS_INDEX 1
33 #define CONFIG_BAUDRATE 115200
35 #define CONFIG_BOOTDELAY 5
37 #define CONFIG_IPADDR 192.168.0.2
38 #define CONFIG_NETMASK 255.255.255.0
39 #define CONFIG_SERVERIP 192.168.0.1
41 #define CONFIG_BOOTARGS \
42 "console=ttyS0,115200 " \
43 "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
44 "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
45 "kvme080:eth0:none " \
46 "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
48 #define CONFIG_BOOTCOMMAND \
49 "tftp 800000 kvme080/uImage; " \
52 #define CONFIG_LOADADDR 800000
54 #define CONFIG_BOARD_EARLY_INIT_F
55 #define CONFIG_BOARD_EARLY_INIT_R
56 #define CONFIG_MISC_INIT_R
58 #define CONFIG_LOADS_ECHO 1
59 #undef CFG_LOADS_BAUD_CHANGE
61 #undef CONFIG_WATCHDOG
63 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
65 #define CONFIG_MAC_PARTITION
66 #define CONFIG_DOS_PARTITION
68 #define CONFIG_RTC_DS164x
72 * Command line configuration.
74 #include <config_cmd_default.h>
76 #define CONFIG_CMD_ASKENV
77 #define CONFIG_CMD_CACHE
78 #define CONFIG_CMD_DATE
79 #define CONFIG_CMD_DHCP
80 #define CONFIG_CMD_DIAG
81 #define CONFIG_CMD_EEPROM
82 #define CONFIG_CMD_ELF
83 #define CONFIG_CMD_I2C
84 #define CONFIG_CMD_JFFS2
85 #define CONFIG_CMD_NFS
86 #define CONFIG_CMD_PCI
87 #define CONFIG_CMD_PING
88 #define CONFIG_CMD_SDRAM
89 #define CONFIG_CMD_SNTP
92 #define CONFIG_NETCONSOLE
95 #define CFG_PROMPT "=> "
96 #define CFG_CBSIZE 256
97 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
98 #define CFG_MAXARGS 16
99 #define CFG_BARGSIZE CFG_CBSIZE
101 #define CFG_MEMTEST_START 0x00400000
102 #define CFG_MEMTEST_END 0x07C00000
104 #define CFG_LOAD_ADDR 0x00100000
107 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
109 #define CFG_INIT_RAM_ADDR 0x40000000
110 #define CFG_INIT_RAM_END 0x1000
111 #define CFG_GBL_DATA_SIZE 128
112 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
114 #define CFG_SDRAM_BASE 0x00000000
115 #define CFG_FLASH_BASE 0x7C000000
116 #define CFG_EUMB_ADDR 0xFC000000
117 #define CFG_NVRAM_BASE_ADDR 0xFF000000
118 #define CFG_NS16550_COM1 0xFF080000
119 #define CFG_NS16550_COM2 0xFF080010
120 #define CFG_NS16550_COM3 0xFF080020
121 #define CFG_NS16550_COM4 0xFF080030
122 #define CFG_RESET_ADDRESS 0xFFF00100
124 #define CFG_MAX_RAM_SIZE 0x20000000
125 #define CFG_FLASH_SIZE (16 * 1024 * 1024)
126 #define CFG_NVRAM_SIZE 0x7FFF8
128 #define CONFIG_VERY_BIG_RAM
130 #define CFG_MONITOR_LEN 0x00040000
131 #define CFG_MONITOR_BASE TEXT_BASE
132 #define CFG_MALLOC_LEN (512 << 10)
134 #define CFG_BOOTMAPSZ (8 << 20)
136 #define CFG_FLASH_CFI
137 #define CFG_FLASH_CFI_DRIVER
138 #define CFG_FLASH_USE_BUFFER_WRITE
139 #define CFG_FLASH_PROTECTION
140 #define CFG_FLASH_EMPTY_INFO
141 #define CFG_FLASH_PROTECT_CLEAR
143 #define CFG_MAX_FLASH_BANKS 1
144 #define CFG_MAX_FLASH_SECT 256
146 #define CFG_FLASH_ERASE_TOUT 120000
147 #define CFG_FLASH_WRITE_TOUT 500
149 #define CFG_JFFS2_FIRST_BANK 0
150 #define CFG_JFFS2_NUM_BANKS 1
152 #define CFG_ENV_IS_IN_NVRAM 1
153 #define CONFIG_ENV_OVERWRITE 1
154 #define CFG_NVRAM_ACCESS_ROUTINE
155 #define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
156 #define CFG_ENV_SIZE 0x400
157 #define CFG_ENV_OFFSET 0
160 #define CFG_NS16550_SERIAL
161 #define CFG_NS16550_REG_SIZE 1
162 #define CFG_NS16550_CLK 14745600
165 #define CONFIG_PCI_PNP
167 #define CONFIG_NET_MULTI
168 #define CONFIG_EEPRO100
169 #define CONFIG_EEPRO100_SROM_WRITE
171 #define CFG_RX_ETH_BUFFER 8
173 #define CONFIG_HARD_I2C 1
174 #define CFG_I2C_SPEED 400000
175 #define CFG_I2C_SLAVE 0x7F
177 #define CFG_I2C_EEPROM_ADDR 0x57
178 #define CFG_I2C_EEPROM_ADDR_LEN 1
179 #define CFG_EEPROM_PAGE_WRITE_BITS 3
180 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
182 #define CONFIG_SYS_CLK_FREQ 33333333
184 #define CFG_CACHELINE_SIZE 32
185 #if defined(CONFIG_CMD_KGDB)
186 # define CFG_CACHELINE_SHIFT 5
189 #define CFG_DLL_EXTEND 0x00
190 #define CFG_PCI_HOLD_DEL 0x20
192 #define CFG_ROMNAL 15
193 #define CFG_ROMFAL 31
195 #define CFG_REFINT 430
197 #define CFG_DBUS_SIZE2 1
199 #define CFG_BSTOPRE 121
202 #define CFG_PRETOACT 3
203 #define CFG_ACTTOPRE 5
205 #define CFG_SDMODE_CAS_LAT 3
206 #define CFG_SDMODE_WRAP 0
208 #define CFG_REGISTERD_TYPE_BUFFER 1
210 #define CFG_REGDIMM 0
212 #define CFG_BANK0_START 0x00000000
213 #define CFG_BANK0_END (0x4000000 - 1)
214 #define CFG_BANK0_ENABLE 1
215 #define CFG_BANK1_START 0x04000000
216 #define CFG_BANK1_END (0x8000000 - 1)
217 #define CFG_BANK1_ENABLE 1
218 #define CFG_BANK2_START 0x3ff00000
219 #define CFG_BANK2_END 0x3fffffff
220 #define CFG_BANK2_ENABLE 0
221 #define CFG_BANK3_START 0x3ff00000
222 #define CFG_BANK3_END 0x3fffffff
223 #define CFG_BANK3_ENABLE 0
224 #define CFG_BANK4_START 0x00000000
225 #define CFG_BANK4_END 0x00000000
226 #define CFG_BANK4_ENABLE 0
227 #define CFG_BANK5_START 0x00000000
228 #define CFG_BANK5_END 0x00000000
229 #define CFG_BANK5_ENABLE 0
230 #define CFG_BANK6_START 0x00000000
231 #define CFG_BANK6_END 0x00000000
232 #define CFG_BANK6_ENABLE 0
233 #define CFG_BANK7_START 0x00000000
234 #define CFG_BANK7_END 0x00000000
235 #define CFG_BANK7_ENABLE 0
237 #define CFG_BANK_ENABLE 0x03
239 #define CFG_ODCR 0x75
240 #define CFG_PGMAX 0x32
242 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
243 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
245 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
246 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
248 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
249 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
251 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
252 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
254 #define CFG_DBAT0L CFG_IBAT0L
255 #define CFG_DBAT0U CFG_IBAT0U
256 #define CFG_DBAT1L CFG_IBAT1L
257 #define CFG_DBAT1U CFG_IBAT1U
258 #define CFG_DBAT2L CFG_IBAT2L
259 #define CFG_DBAT2U CFG_IBAT2U
260 #define CFG_DBAT3L CFG_IBAT3L
261 #define CFG_DBAT3U CFG_IBAT3U
263 #define BOOTFLAG_COLD 0x01
264 #define BOOTFLAG_WARM 0x02
266 #endif /* __CONFIG_H */