git.sur5r.net Git - u-boot/blob - include/configs/ls1012afrdm.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1012ARDB_H__
   8 #define __LS1012ARDB_H__
   9
  10 #include "ls1012a_common.h"
  11
  12 /* DDR */
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  14 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  15 #define CONFIG_NR_DRAM_BANKS            2
  16 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  17 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  18 #define CONFIG_CMD_MEMINFO
  19 #define CONFIG_CMD_MEMTEST
  20 #define CONFIG_SYS_MEMTEST_START        0x80000000
  21 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
  22
  23 /* DDR board-specific timing parameters */
  24 #define CONFIG_MMDC_MDCTL       0x04180000
  25 #define CONFIG_MMDC_MDPDC       0x00030035
  26 #define CONFIG_MMDC_MDOTC       0x12554000
  27 #define CONFIG_MMDC_MDCFG0      0xbabf7954
  28 #define CONFIG_MMDC_MDCFG1      0xdb328f64
  29 #define CONFIG_MMDC_MDCFG2      0x01ff00db
  30 #define CONFIG_MMDC_MDMISC      0x00001680
  31 #define CONFIG_MMDC_MDREF       0x0f3c8000
  32 #define CONFIG_MMDC_MDRWD       0x00002000
  33 #define CONFIG_MMDC_MDOR        0x00bf1023
  34 #define CONFIG_MMDC_MDASP       0x0000003f
  35 #define CONFIG_MMDC_MPODTCTRL   0x0000022a
  36 #define CONFIG_MMDC_MPZQHWCTRL  0xa1390003
  37
  38
  39 /*
  40 * USB
  41 */
  42 #define CONFIG_HAS_FSL_XHCI_USB
  43
  44 #ifdef CONFIG_HAS_FSL_XHCI_USB
  45 #define CONFIG_USB_XHCI_FSL
  46 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
  47 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
  48 #endif
  49
  50 #define CONFIG_CMD_MEMINFO
  51 #define CONFIG_CMD_MEMTEST
  52 #define CONFIG_SYS_MEMTEST_START        0x80000000
  53 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
  54
  55 #endif /* __LS1012ARDB_H__ */