2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1012AQDS_H__
8 #define __LS1012AQDS_H__
10 #include "ls1012a_common.h"
13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
15 #define CONFIG_NR_DRAM_BANKS 2
16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
17 #define CONFIG_CMD_MEMINFO
18 #define CONFIG_CMD_MEMTEST
19 #define CONFIG_SYS_MEMTEST_START 0x80000000
20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
22 /* DDR board-specific timing parameters */
23 #define CONFIG_MMDC_MDCTL 0x05180000
24 #define CONFIG_MMDC_MDPDC 0x00030035
25 #define CONFIG_MMDC_MDOTC 0x12554000
26 #define CONFIG_MMDC_MDCFG0 0xbabf7954
27 #define CONFIG_MMDC_MDCFG1 0xdb328f64
28 #define CONFIG_MMDC_MDCFG2 0x01ff00db
29 #define CONFIG_MMDC_MDMISC 0x00001680
30 #define CONFIG_MMDC_MDREF 0x0f3c8000
31 #define CONFIG_MMDC_MDRWD 0x00002000
32 #define CONFIG_MMDC_MDOR 0x00bf1023
33 #define CONFIG_MMDC_MDASP 0x0000003f
34 #define CONFIG_MMDC_MPODTCTRL 0x0000022a
35 #define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
41 #define CONFIG_FSL_QIXIS
43 #ifdef CONFIG_FSL_QIXIS
44 #define CONFIG_QIXIS_I2C_ACCESS
45 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
46 #define QIXIS_LBMAP_BRDCFG_REG 0x04
47 #define QIXIS_LBMAP_SWITCH 6
48 #define QIXIS_LBMAP_MASK 0x08
49 #define QIXIS_LBMAP_SHIFT 0
50 #define QIXIS_LBMAP_DFLTBANK 0x00
51 #define QIXIS_LBMAP_ALTBANK 0x08
52 #define QIXIS_RST_CTL_RESET 0x31
53 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
54 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
55 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
61 #define I2C_MUX_PCA_ADDR_PRI 0x77
62 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
63 #define I2C_RETIMER_ADDR 0x18
64 #define I2C_MUX_CH_DEFAULT 0x8
65 #define I2C_MUX_CH_CH7301 0xC
66 #define I2C_MUX_CH5 0xD
67 #define I2C_MUX_CH7 0xF
69 #define I2C_MUX_CH_VOL_MONITOR 0xa
75 #define CONFIG_RTC_PCF8563 1
76 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
77 #define CONFIG_CMD_DATE
80 #define CONFIG_ID_EEPROM
81 #define CONFIG_CMD_EEPROM
82 #define CONFIG_SYS_I2C_EEPROM_NXID
83 #define CONFIG_SYS_EEPROM_BUS_NUM 0
84 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
85 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
86 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
87 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
90 /* Voltage monitor on channel 2*/
91 #define I2C_VOL_MONITOR_ADDR 0x40
92 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
93 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
94 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
97 #define CONFIG_FSL_DSPI1
98 #define CONFIG_DEFAULT_SPI_BUS 1
100 #define CONFIG_CMD_SPI
101 #define MMAP_DSPI DSPI1_BASE_ADDR
103 #define CONFIG_SYS_DSPI_CTAR0 1
105 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
106 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
107 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
109 #define CONFIG_SPI_FLASH_SST /* cs1 */
111 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
112 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
113 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
115 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */
117 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
118 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
119 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
121 #define CONFIG_SPI_FLASH_EON /* cs3 */
123 #define CONFIG_SF_DEFAULT_SPEED 10000000
124 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
125 #define CONFIG_SF_DEFAULT_BUS 1
126 #define CONFIG_SF_DEFAULT_CS 0
131 /* EHCI Support - disbaled by default */
132 /*#define CONFIG_HAS_FSL_DR_USB*/
134 #ifdef CONFIG_HAS_FSL_DR_USB
135 #define CONFIG_USB_EHCI
136 #define CONFIG_USB_EHCI_FSL
137 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
140 /*XHCI Support - enabled by default*/
141 #define CONFIG_HAS_FSL_XHCI_USB
143 #ifdef CONFIG_HAS_FSL_XHCI_USB
144 #define CONFIG_USB_XHCI_FSL
145 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
146 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
152 #define CONFIG_FSL_ESDHC
153 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
154 #define CONFIG_GENERIC_MMC
155 #define CONFIG_DOS_PARTITION
159 #define CONFIG_LIBATA
161 #define CONFIG_SCSI_AHCI
162 #define CONFIG_SCSI_AHCI_PLAT
163 #define CONFIG_CMD_SCSI
164 #define CONFIG_DOS_PARTITION
165 #define CONFIG_BOARD_LATE_INIT
167 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
169 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
170 #define CONFIG_SYS_SCSI_MAX_LUN 1
171 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
172 CONFIG_SYS_SCSI_MAX_LUN)
173 #define CONFIG_PCI /* Enable PCI/PCIE */
174 #define CONFIG_PCIE1 /* PCIE controller 1 */
175 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
176 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
178 #define CONFIG_SYS_PCI_64BIT
180 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
181 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
182 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
183 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
185 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
186 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
187 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
189 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
190 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
191 #define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
193 #define CONFIG_NET_MULTI
194 #define CONFIG_PCI_PNP
195 #define CONFIG_PCI_SCAN_SHOW
196 #define CONFIG_CMD_PCI
198 #define CONFIG_CMD_MEMINFO
199 #define CONFIG_CMD_MEMTEST
200 #define CONFIG_SYS_MEMTEST_START 0x80000000
201 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
203 #define CONFIG_MISC_INIT_R
205 #endif /* __LS1012AQDS_H__ */