2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <config_cmd_default.h>
12 #define CONFIG_LS102XA
14 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
23 * Size of malloc() pool
25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
31 * Generic Timer Definitions
33 #define GENERIC_TIMER_CLK 12500000
36 unsigned long get_board_sys_clk(void);
37 unsigned long get_board_ddr_clk(void);
40 #ifdef CONFIG_QSPI_BOOT
41 #define CONFIG_SYS_CLK_FREQ 100000000
42 #define CONFIG_DDR_CLK_FREQ 100000000
43 #define CONFIG_QIXIS_I2C_ACCESS
45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
49 #ifdef CONFIG_RAMBOOT_PBL
50 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
55 #define CONFIG_SPL_FRAMEWORK
56 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
57 #define CONFIG_SPL_LIBCOMMON_SUPPORT
58 #define CONFIG_SPL_LIBGENERIC_SUPPORT
59 #define CONFIG_SPL_ENV_SUPPORT
60 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
61 #define CONFIG_SPL_I2C_SUPPORT
62 #define CONFIG_SPL_WATCHDOG_SUPPORT
63 #define CONFIG_SPL_SERIAL_SUPPORT
64 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
65 #define CONFIG_SPL_MMC_SUPPORT
66 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
67 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
69 #define CONFIG_SPL_TEXT_BASE 0x10000000
70 #define CONFIG_SPL_MAX_SIZE 0x1a000
71 #define CONFIG_SPL_STACK 0x1001d000
72 #define CONFIG_SPL_PAD_TO 0x1c000
73 #define CONFIG_SYS_TEXT_BASE 0x82000000
75 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
76 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
77 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
78 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
79 #define CONFIG_SYS_MONITOR_LEN 0x80000
82 #ifdef CONFIG_QSPI_BOOT
83 #define CONFIG_SYS_TEXT_BASE 0x40010000
84 #define CONFIG_SYS_NO_FLASH
87 #ifndef CONFIG_SYS_TEXT_BASE
88 #define CONFIG_SYS_TEXT_BASE 0x67f80000
91 #define CONFIG_NR_DRAM_BANKS 1
93 #define CONFIG_DDR_SPD
94 #define SPD_EEPROM_ADDRESS 0x51
95 #define CONFIG_SYS_SPD_BUS_NUM 0
97 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
98 #ifndef CONFIG_SYS_FSL_DDR4
99 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
100 #define CONFIG_SYS_DDR_RAW_TIMING
102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
103 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_DDR_ECC
109 #ifdef CONFIG_DDR_ECC
110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
111 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
114 #define CONFIG_SYS_HAS_SERDES
116 #define CONFIG_FSL_CAAM /* Enable CAAM */
118 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
119 !defined(CONFIG_QSPI_BOOT)
126 #ifndef CONFIG_QSPI_BOOT
127 #define CONFIG_FSL_IFC
128 #define CONFIG_SYS_FLASH_BASE 0x60000000
129 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
131 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
132 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
133 CSPR_PORT_SIZE_16 | \
136 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
137 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
139 CSPR_PORT_SIZE_16 | \
142 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
144 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
146 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
147 FTIM0_NOR_TEADC(0x5) | \
148 FTIM0_NOR_TEAHC(0x5))
149 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
150 FTIM1_NOR_TRAD_NOR(0x1a) | \
151 FTIM1_NOR_TSEQRAD_NOR(0x13))
152 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
153 FTIM2_NOR_TCH(0x4) | \
154 FTIM2_NOR_TWPH(0xe) | \
156 #define CONFIG_SYS_NOR_FTIM3 0
158 #define CONFIG_FLASH_CFI_DRIVER
159 #define CONFIG_SYS_FLASH_CFI
160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
161 #define CONFIG_SYS_FLASH_QUIET_TEST
162 #define CONFIG_FLASH_SHOW_PROGRESS 45
163 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
164 #define CONFIG_SYS_WRITE_SWAPPED_DATA
166 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
167 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
171 #define CONFIG_SYS_FLASH_EMPTY_INFO
172 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
173 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
176 * NAND Flash Definitions
178 #define CONFIG_NAND_FSL_IFC
180 #define CONFIG_SYS_NAND_BASE 0x7e800000
181 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
183 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
185 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
189 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
190 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
191 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
192 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
193 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
194 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
195 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
196 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
198 #define CONFIG_SYS_NAND_ONFI_DETECTION
200 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
201 FTIM0_NAND_TWP(0x18) | \
202 FTIM0_NAND_TWCHT(0x7) | \
204 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
205 FTIM1_NAND_TWBE(0x39) | \
206 FTIM1_NAND_TRR(0xe) | \
207 FTIM1_NAND_TRP(0x18))
208 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
209 FTIM2_NAND_TREH(0xa) | \
210 FTIM2_NAND_TWHRE(0x1e))
211 #define CONFIG_SYS_NAND_FTIM3 0x0
213 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
214 #define CONFIG_SYS_MAX_NAND_DEVICE 1
215 #define CONFIG_MTD_NAND_VERIFY_WRITE
216 #define CONFIG_CMD_NAND
218 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
224 #define CONFIG_FSL_QIXIS
226 #ifdef CONFIG_FSL_QIXIS
227 #define QIXIS_BASE 0x7fb00000
228 #define QIXIS_BASE_PHYS QIXIS_BASE
229 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
230 #define QIXIS_LBMAP_SWITCH 6
231 #define QIXIS_LBMAP_MASK 0x0f
232 #define QIXIS_LBMAP_SHIFT 0
233 #define QIXIS_LBMAP_DFLTBANK 0x00
234 #define QIXIS_LBMAP_ALTBANK 0x04
235 #define QIXIS_RST_CTL_RESET 0x44
236 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
237 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
238 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
240 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
241 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
245 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
246 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
247 CSOR_NOR_NOR_MODE_AVD_NOR | \
251 * QIXIS Timing parameters for IFC GPCM
253 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
254 FTIM0_GPCM_TEADC(0xe) | \
255 FTIM0_GPCM_TEAHC(0xe))
256 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
257 FTIM1_GPCM_TRAD(0x1f))
258 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
259 FTIM2_GPCM_TCH(0xe) | \
260 FTIM2_GPCM_TWP(0xf0))
261 #define CONFIG_SYS_FPGA_FTIM3 0x0
264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
280 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
281 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
282 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
283 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
284 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
285 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
286 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
287 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
288 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
289 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
290 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
291 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
292 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
293 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
294 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
295 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
300 #define CONFIG_CONS_INDEX 1
301 #define CONFIG_SYS_NS16550
302 #define CONFIG_SYS_NS16550_SERIAL
303 #define CONFIG_SYS_NS16550_REG_SIZE 1
304 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
306 #define CONFIG_BAUDRATE 115200
311 #define CONFIG_CMD_I2C
312 #define CONFIG_SYS_I2C
313 #define CONFIG_SYS_I2C_MXC
316 * I2C bus multiplexer
318 #define I2C_MUX_PCA_ADDR_PRI 0x77
319 #define I2C_MUX_CH_DEFAULT 0x8
325 #define CONFIG_CMD_MMC
326 #define CONFIG_FSL_ESDHC
327 #define CONFIG_GENERIC_MMC
329 #define CONFIG_CMD_FAT
330 #define CONFIG_DOS_PARTITION
333 #ifdef CONFIG_QSPI_BOOT
334 #define CONFIG_FSL_QSPI
335 #define QSPI0_AMBA_BASE 0x40000000
336 #define FSL_QSPI_FLASH_SIZE (1 << 24)
337 #define FSL_QSPI_FLASH_NUM 2
339 #define CONFIG_CMD_SF
340 #define CONFIG_SPI_FLASH
341 #define CONFIG_SPI_FLASH_SPANSION
347 #define CONFIG_HAS_FSL_DR_USB
349 #ifdef CONFIG_HAS_FSL_DR_USB
350 #define CONFIG_USB_EHCI
352 #ifdef CONFIG_USB_EHCI
353 #define CONFIG_CMD_USB
354 #define CONFIG_USB_STORAGE
355 #define CONFIG_USB_EHCI_FSL
356 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
357 #define CONFIG_CMD_EXT2
364 #define CONFIG_TSEC_ENET
366 #ifdef CONFIG_TSEC_ENET
368 #define CONFIG_MII_DEFAULT_TSEC 3
369 #define CONFIG_TSEC1 1
370 #define CONFIG_TSEC1_NAME "eTSEC1"
371 #define CONFIG_TSEC2 1
372 #define CONFIG_TSEC2_NAME "eTSEC2"
373 #define CONFIG_TSEC3 1
374 #define CONFIG_TSEC3_NAME "eTSEC3"
376 #define TSEC1_PHY_ADDR 1
377 #define TSEC2_PHY_ADDR 2
378 #define TSEC3_PHY_ADDR 3
380 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
381 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
382 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
384 #define TSEC1_PHYIDX 0
385 #define TSEC2_PHYIDX 0
386 #define TSEC3_PHYIDX 0
388 #define CONFIG_ETHPRIME "eTSEC1"
390 #define CONFIG_PHY_GIGE
391 #define CONFIG_PHYLIB
392 #define CONFIG_PHY_REALTEK
394 #define CONFIG_HAS_ETH0
395 #define CONFIG_HAS_ETH1
396 #define CONFIG_HAS_ETH2
398 #define CONFIG_FSL_SGMII_RISER 1
399 #define SGMII_RISER_PHY_OFFSET 0x1b
401 #ifdef CONFIG_FSL_SGMII_RISER
402 #define CONFIG_SYS_TBIPA_VALUE 8
408 #define CONFIG_PCI /* Enable PCI/PCIE */
409 #define CONFIG_PCIE1 /* PCIE controler 1 */
410 #define CONFIG_PCIE2 /* PCIE controler 2 */
411 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
412 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
414 #define CONFIG_CMD_PING
415 #define CONFIG_CMD_DHCP
416 #define CONFIG_CMD_MII
417 #define CONFIG_CMD_NET
419 #define CONFIG_CMDLINE_TAG
420 #define CONFIG_CMDLINE_EDITING
422 #ifdef CONFIG_QSPI_BOOT
423 #undef CONFIG_CMD_IMLS
425 #define CONFIG_CMD_IMLS
428 #define CONFIG_HWCONFIG
429 #define HWCONFIG_BUFFER_SIZE 128
431 #define CONFIG_BOOTDELAY 3
433 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
435 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
437 "fdt_high=0xcfffffff\0" \
438 "initrd_high=0xcfffffff\0" \
439 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
442 * Miscellaneous configurable options
444 #define CONFIG_SYS_LONGHELP /* undef to save memory */
445 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
446 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
447 #define CONFIG_AUTO_COMPLETE
448 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
449 #define CONFIG_SYS_PBSIZE \
450 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
451 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
452 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
454 #define CONFIG_CMD_ENV_EXISTS
455 #define CONFIG_CMD_GREPENV
456 #define CONFIG_CMD_MEMINFO
457 #define CONFIG_CMD_MEMTEST
458 #define CONFIG_SYS_MEMTEST_START 0x80000000
459 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
461 #define CONFIG_SYS_LOAD_ADDR 0x82000000
465 * The stack sizes are set up in start.S using the settings below
467 #define CONFIG_STACKSIZE (30 * 1024)
469 #define CONFIG_SYS_INIT_SP_OFFSET \
470 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
471 #define CONFIG_SYS_INIT_SP_ADDR \
472 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
474 #ifdef CONFIG_SPL_BUILD
475 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
477 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
483 #define CONFIG_ENV_OVERWRITE
485 #if defined(CONFIG_SD_BOOT)
486 #define CONFIG_ENV_OFFSET 0x100000
487 #define CONFIG_ENV_IS_IN_MMC
488 #define CONFIG_SYS_MMC_ENV_DEV 0
489 #define CONFIG_ENV_SIZE 0x2000
490 #elif defined(CONFIG_QSPI_BOOT)
491 #define CONFIG_ENV_IS_IN_SPI_FLASH
492 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
493 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
494 #define CONFIG_ENV_SECT_SIZE 0x10000
496 #define CONFIG_ENV_IS_IN_FLASH
497 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
498 #define CONFIG_ENV_SIZE 0x2000
499 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
502 #define CONFIG_OF_LIBFDT
503 #define CONFIG_OF_BOARD_SETUP
504 #define CONFIG_CMD_BOOTZ
506 #define CONFIG_MISC_INIT_R
508 /* Hash command with SHA acceleration supported in hardware */
509 #define CONFIG_CMD_HASH
510 #define CONFIG_SHA_HW_ACCEL
512 #ifdef CONFIG_SECURE_BOOT
513 #define CONFIG_CMD_BLOB