2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_ARMV7_PSCI
13 #define CONFIG_ARMV7_PSCI_1_0
14 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
16 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
18 #define CONFIG_SYS_FSL_CLK
20 #define CONFIG_DISPLAY_CPUINFO
21 #define CONFIG_DISPLAY_BOARDINFO
23 #define CONFIG_SKIP_LOWLEVEL_INIT
24 #define CONFIG_BOARD_EARLY_INIT_F
25 #define CONFIG_DEEP_SLEEP
26 #ifdef CONFIG_DEEP_SLEEP
27 #define CONFIG_SILENT_CONSOLE
31 * Size of malloc() pool
33 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
35 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
36 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
43 * EHCI Support - disbaled by default as
44 * there is no signal coming out of soc on
45 * this board for this controller. However,
46 * the silicon still has this controller,
47 * and anyone can use this controller by
48 * taking signals out on their board.
51 /*#define CONFIG_HAS_FSL_DR_USB*/
53 #ifdef CONFIG_HAS_FSL_DR_USB
54 #define CONFIG_USB_EHCI
55 #define CONFIG_USB_EHCI_FSL
56 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
59 /* XHCI Support - enabled by default */
60 #define CONFIG_HAS_FSL_XHCI_USB
62 #ifdef CONFIG_HAS_FSL_XHCI_USB
63 #define CONFIG_USB_XHCI_FSL
64 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
65 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
68 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
69 #define CONFIG_USB_STORAGE
73 * Generic Timer Definitions
75 #define GENERIC_TIMER_CLK 12500000
77 #define CONFIG_SYS_CLK_FREQ 100000000
78 #define CONFIG_DDR_CLK_FREQ 100000000
80 #define DDR_SDRAM_CFG 0x470c0008
81 #define DDR_CS0_BNDS 0x008000bf
82 #define DDR_CS0_CONFIG 0x80014302
83 #define DDR_TIMING_CFG_0 0x50550004
84 #define DDR_TIMING_CFG_1 0xbcb38c56
85 #define DDR_TIMING_CFG_2 0x0040d120
86 #define DDR_TIMING_CFG_3 0x010e1000
87 #define DDR_TIMING_CFG_4 0x00000001
88 #define DDR_TIMING_CFG_5 0x03401400
89 #define DDR_SDRAM_CFG_2 0x00401010
90 #define DDR_SDRAM_MODE 0x00061c60
91 #define DDR_SDRAM_MODE_2 0x00180000
92 #define DDR_SDRAM_INTERVAL 0x18600618
93 #define DDR_DDR_WRLVL_CNTL 0x8655f605
94 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
95 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
96 #define DDR_DDR_CDR1 0x80040000
97 #define DDR_DDR_CDR2 0x00000001
98 #define DDR_SDRAM_CLK_CNTL 0x02000000
99 #define DDR_DDR_ZQ_CNTL 0x89080600
100 #define DDR_CS0_CONFIG_2 0
101 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
102 #define SDRAM_CFG2_D_INIT 0x00000010
103 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
104 #define SDRAM_CFG2_FRC_SR 0x80000000
105 #define SDRAM_CFG_BI 0x00000001
107 #ifdef CONFIG_RAMBOOT_PBL
108 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
111 #ifdef CONFIG_SD_BOOT
112 #ifdef CONFIG_SD_BOOT_QSPI
113 #define CONFIG_SYS_FSL_PBL_RCW \
114 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
116 #define CONFIG_SYS_FSL_PBL_RCW \
117 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
119 #define CONFIG_SPL_FRAMEWORK
120 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
121 #define CONFIG_SPL_LIBCOMMON_SUPPORT
122 #define CONFIG_SPL_LIBGENERIC_SUPPORT
123 #define CONFIG_SPL_ENV_SUPPORT
124 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
125 #define CONFIG_SPL_I2C_SUPPORT
126 #define CONFIG_SPL_WATCHDOG_SUPPORT
127 #define CONFIG_SPL_SERIAL_SUPPORT
128 #define CONFIG_SPL_MMC_SUPPORT
129 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
131 #ifdef CONFIG_SECURE_BOOT
132 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
134 * HDR would be appended at end of image and copied to DDR along
137 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
138 (CONFIG_U_BOOT_HDR_SIZE / 512)
140 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
141 #endif /* ifdef CONFIG_SECURE_BOOT */
143 #define CONFIG_SPL_TEXT_BASE 0x10000000
144 #define CONFIG_SPL_MAX_SIZE 0x1a000
145 #define CONFIG_SPL_STACK 0x1001d000
146 #define CONFIG_SPL_PAD_TO 0x1c000
147 #define CONFIG_SYS_TEXT_BASE 0x82000000
149 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
150 CONFIG_SYS_MONITOR_LEN)
151 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
152 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
153 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
155 #ifdef CONFIG_U_BOOT_HDR_SIZE
157 * HDR would be appended at end of image and copied to DDR along
158 * with U-Boot image. Here u-boot max. size is 512K. So if binary
159 * size increases then increase this size in case of secure boot as
160 * it uses raw u-boot image instead of fit image.
162 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
164 #define CONFIG_SYS_MONITOR_LEN 0x80000
165 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
168 #ifdef CONFIG_QSPI_BOOT
169 #define CONFIG_SYS_TEXT_BASE 0x40010000
172 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
173 #define CONFIG_SYS_NO_FLASH
176 #ifndef CONFIG_SYS_TEXT_BASE
177 #define CONFIG_SYS_TEXT_BASE 0x60100000
180 #define CONFIG_NR_DRAM_BANKS 1
181 #define PHYS_SDRAM 0x80000000
182 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
184 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
185 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
187 #define CONFIG_SYS_HAS_SERDES
189 #define CONFIG_FSL_CAAM /* Enable CAAM */
191 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
192 !defined(CONFIG_QSPI_BOOT)
199 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
200 #define CONFIG_FSL_IFC
201 #define CONFIG_SYS_FLASH_BASE 0x60000000
202 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
205 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
206 CSPR_PORT_SIZE_16 | \
209 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
211 /* NOR Flash Timing Params */
212 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
214 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
215 FTIM0_NOR_TEADC(0x5) | \
216 FTIM0_NOR_TAVDS(0x0) | \
217 FTIM0_NOR_TEAHC(0x5))
218 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
219 FTIM1_NOR_TRAD_NOR(0x1A) | \
220 FTIM1_NOR_TSEQRAD_NOR(0x13))
221 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
222 FTIM2_NOR_TCH(0x4) | \
223 FTIM2_NOR_TWP(0x1c) | \
224 FTIM2_NOR_TWPH(0x0e))
225 #define CONFIG_SYS_NOR_FTIM3 0
227 #define CONFIG_FLASH_CFI_DRIVER
228 #define CONFIG_SYS_FLASH_CFI
229 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
230 #define CONFIG_SYS_FLASH_QUIET_TEST
231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
234 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
238 #define CONFIG_SYS_FLASH_EMPTY_INFO
239 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
241 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
242 #define CONFIG_SYS_WRITE_SWAPPED_DATA
247 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
248 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
250 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
251 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
255 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
256 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
257 CSOR_NOR_NOR_MODE_AVD_NOR | \
260 /* CPLD Timing parameters for IFC GPCM */
261 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
262 FTIM0_GPCM_TEADC(0xf) | \
263 FTIM0_GPCM_TEAHC(0xf))
264 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
265 FTIM1_GPCM_TRAD(0x3f))
266 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
267 FTIM2_GPCM_TCH(0xf) | \
268 FTIM2_GPCM_TWP(0xff))
269 #define CONFIG_SYS_FPGA_FTIM3 0x0
270 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
271 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
272 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
273 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
278 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
279 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
281 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
282 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
283 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
284 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
285 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
291 #define CONFIG_LPUART_32B_REG
293 #define CONFIG_CONS_INDEX 1
294 #define CONFIG_SYS_NS16550_SERIAL
295 #ifndef CONFIG_DM_SERIAL
296 #define CONFIG_SYS_NS16550_REG_SIZE 1
298 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
301 #define CONFIG_BAUDRATE 115200
306 #define CONFIG_SYS_I2C
307 #define CONFIG_SYS_I2C_MXC
308 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
309 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
310 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
313 #define CONFIG_ID_EEPROM
314 #define CONFIG_SYS_I2C_EEPROM_NXID
315 #define CONFIG_SYS_EEPROM_BUS_NUM 1
316 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
317 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
318 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
325 #define CONFIG_FSL_ESDHC
326 #define CONFIG_GENERIC_MMC
328 #define CONFIG_DOS_PARTITION
331 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
333 #define QSPI0_AMBA_BASE 0x40000000
334 #define FSL_QSPI_FLASH_SIZE (1 << 24)
335 #define FSL_QSPI_FLASH_NUM 2
341 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
342 #define CONFIG_DM_SPI_FLASH
348 #define CONFIG_FSL_DCU_FB
350 #ifdef CONFIG_FSL_DCU_FB
352 #define CONFIG_CMD_BMP
353 #define CONFIG_CFB_CONSOLE
354 #define CONFIG_VGA_AS_SINGLE_DEVICE
355 #define CONFIG_VIDEO_LOGO
356 #define CONFIG_VIDEO_BMP_LOGO
357 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
359 #define CONFIG_FSL_DCU_SII9022A
360 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
361 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
367 #define CONFIG_TSEC_ENET
369 #ifdef CONFIG_TSEC_ENET
371 #define CONFIG_MII_DEFAULT_TSEC 1
372 #define CONFIG_TSEC1 1
373 #define CONFIG_TSEC1_NAME "eTSEC1"
374 #define CONFIG_TSEC2 1
375 #define CONFIG_TSEC2_NAME "eTSEC2"
376 #define CONFIG_TSEC3 1
377 #define CONFIG_TSEC3_NAME "eTSEC3"
379 #define TSEC1_PHY_ADDR 2
380 #define TSEC2_PHY_ADDR 0
381 #define TSEC3_PHY_ADDR 1
383 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
384 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
385 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
387 #define TSEC1_PHYIDX 0
388 #define TSEC2_PHYIDX 0
389 #define TSEC3_PHYIDX 0
391 #define CONFIG_ETHPRIME "eTSEC1"
393 #define CONFIG_PHY_GIGE
394 #define CONFIG_PHYLIB
395 #define CONFIG_PHY_ATHEROS
397 #define CONFIG_HAS_ETH0
398 #define CONFIG_HAS_ETH1
399 #define CONFIG_HAS_ETH2
403 #define CONFIG_PCI /* Enable PCI/PCIE */
404 #define CONFIG_PCIE1 /* PCIE controller 1 */
405 #define CONFIG_PCIE2 /* PCIE controller 2 */
406 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
407 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
409 #define CONFIG_SYS_PCI_64BIT
411 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
412 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
413 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
414 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
416 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
417 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
418 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
420 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
421 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
422 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
425 #define CONFIG_PCI_PNP
426 #define CONFIG_PCI_SCAN_SHOW
427 #define CONFIG_CMD_PCI
430 #define CONFIG_CMDLINE_TAG
431 #define CONFIG_CMDLINE_EDITING
433 #define CONFIG_ARMV7_NONSEC
434 #define CONFIG_ARMV7_VIRT
435 #define CONFIG_PEN_ADDR_BIG_ENDIAN
436 #define CONFIG_LAYERSCAPE_NS_ACCESS
437 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
438 #define CONFIG_TIMER_CLK_FREQ 12500000
440 #define CONFIG_HWCONFIG
441 #define HWCONFIG_BUFFER_SIZE 256
443 #define CONFIG_FSL_DEVICE_DISABLE
447 #define CONFIG_EXTRA_ENV_SETTINGS \
448 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
449 "initrd_high=0xffffffff\0" \
450 "fdt_high=0xffffffff\0"
452 #define CONFIG_EXTRA_ENV_SETTINGS \
453 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
454 "initrd_high=0xffffffff\0" \
455 "fdt_high=0xffffffff\0"
459 * Miscellaneous configurable options
461 #define CONFIG_SYS_LONGHELP /* undef to save memory */
462 #define CONFIG_AUTO_COMPLETE
463 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
464 #define CONFIG_SYS_PBSIZE \
465 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
466 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
467 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
469 #define CONFIG_SYS_MEMTEST_START 0x80000000
470 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
472 #define CONFIG_SYS_LOAD_ADDR 0x82000000
474 #define CONFIG_LS102XA_STREAM_ID
478 * The stack sizes are set up in start.S using the settings below
480 #define CONFIG_STACKSIZE (30 * 1024)
482 #define CONFIG_SYS_INIT_SP_OFFSET \
483 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
484 #define CONFIG_SYS_INIT_SP_ADDR \
485 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
487 #ifdef CONFIG_SPL_BUILD
488 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
490 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
493 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
498 #define CONFIG_ENV_OVERWRITE
500 #if defined(CONFIG_SD_BOOT)
501 #define CONFIG_ENV_OFFSET 0x100000
502 #define CONFIG_ENV_IS_IN_MMC
503 #define CONFIG_SYS_MMC_ENV_DEV 0
504 #define CONFIG_ENV_SIZE 0x20000
505 #elif defined(CONFIG_QSPI_BOOT)
506 #define CONFIG_ENV_IS_IN_SPI_FLASH
507 #define CONFIG_ENV_SIZE 0x2000
508 #define CONFIG_ENV_OFFSET 0x100000
509 #define CONFIG_ENV_SECT_SIZE 0x10000
511 #define CONFIG_ENV_IS_IN_FLASH
512 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
513 #define CONFIG_ENV_SIZE 0x20000
514 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
517 #define CONFIG_MISC_INIT_R
519 /* Hash command with SHA acceleration supported in hardware */
520 #ifdef CONFIG_FSL_CAAM
521 #define CONFIG_CMD_HASH
522 #define CONFIG_SHA_HW_ACCEL
525 #include <asm/fsl_secure_boot.h>
526 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */