2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <config_cmd_default.h>
12 #define CONFIG_LS102XA
14 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
23 * Size of malloc() pool
25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
31 * Generic Timer Definitions
33 #define GENERIC_TIMER_CLK 12500000
35 #define CONFIG_SYS_CLK_FREQ 100000000
36 #define CONFIG_DDR_CLK_FREQ 100000000
38 #ifndef CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_TEXT_BASE 0x67f80000
42 #define CONFIG_NR_DRAM_BANKS 1
43 #define PHYS_SDRAM 0x80000000
44 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
49 #define CONFIG_SYS_HAS_SERDES
54 #define CONFIG_FSL_IFC
55 #define CONFIG_SYS_FLASH_BASE 0x60000000
56 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
58 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
59 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
65 /* NOR Flash Timing Params */
66 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
68 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
69 FTIM0_NOR_TEADC(0x5) | \
70 FTIM0_NOR_TAVDS(0x0) | \
72 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
73 FTIM1_NOR_TRAD_NOR(0x1A) | \
74 FTIM1_NOR_TSEQRAD_NOR(0x13))
75 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
76 FTIM2_NOR_TCH(0x4) | \
77 FTIM2_NOR_TWP(0x1c) | \
79 #define CONFIG_SYS_NOR_FTIM3 0
81 #define CONFIG_FLASH_CFI_DRIVER
82 #define CONFIG_SYS_FLASH_CFI
83 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
84 #define CONFIG_SYS_FLASH_QUIET_TEST
85 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
87 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
88 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
92 #define CONFIG_SYS_FLASH_EMPTY_INFO
93 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
95 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
99 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
100 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
102 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
103 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
107 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
108 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
109 CSOR_NOR_NOR_MODE_AVD_NOR | \
112 /* CPLD Timing parameters for IFC GPCM */
113 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
114 FTIM0_GPCM_TEADC(0xf) | \
115 FTIM0_GPCM_TEAHC(0xf))
116 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
117 FTIM1_GPCM_TRAD(0x3f))
118 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
119 FTIM2_GPCM_TCH(0xf) | \
120 FTIM2_GPCM_TWP(0xff))
121 #define CONFIG_SYS_FPGA_FTIM3 0x0
122 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
123 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
124 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
125 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
126 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
127 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
128 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
129 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
130 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
131 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
132 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
133 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
134 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
135 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
136 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
137 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
142 #define CONFIG_CONS_INDEX 1
143 #define CONFIG_SYS_NS16550
144 #define CONFIG_SYS_NS16550_SERIAL
145 #define CONFIG_SYS_NS16550_REG_SIZE 1
146 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
148 #define CONFIG_BAUDRATE 115200
153 #define CONFIG_CMD_I2C
154 #define CONFIG_SYS_I2C
155 #define CONFIG_SYS_I2C_MXC
161 #define CONFIG_CMD_MMC
162 #define CONFIG_FSL_ESDHC
163 #define CONFIG_GENERIC_MMC
168 #define CONFIG_FSL_DCU_FB
170 #ifdef CONFIG_FSL_DCU_FB
172 #define CONFIG_CMD_BMP
173 #define CONFIG_CFB_CONSOLE
174 #define CONFIG_VGA_AS_SINGLE_DEVICE
175 #define CONFIG_VIDEO_LOGO
176 #define CONFIG_VIDEO_BMP_LOGO
178 #define CONFIG_FSL_DCU_SII9022A
179 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
180 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
186 #define CONFIG_TSEC_ENET
188 #ifdef CONFIG_TSEC_ENET
190 #define CONFIG_MII_DEFAULT_TSEC 1
191 #define CONFIG_TSEC1 1
192 #define CONFIG_TSEC1_NAME "eTSEC1"
193 #define CONFIG_TSEC2 1
194 #define CONFIG_TSEC2_NAME "eTSEC2"
195 #define CONFIG_TSEC3 1
196 #define CONFIG_TSEC3_NAME "eTSEC3"
198 #define TSEC1_PHY_ADDR 2
199 #define TSEC2_PHY_ADDR 0
200 #define TSEC3_PHY_ADDR 1
202 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
203 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
204 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
206 #define TSEC1_PHYIDX 0
207 #define TSEC2_PHYIDX 0
208 #define TSEC3_PHYIDX 0
210 #define CONFIG_ETHPRIME "eTSEC1"
212 #define CONFIG_PHY_GIGE
213 #define CONFIG_PHYLIB
214 #define CONFIG_PHY_ATHEROS
216 #define CONFIG_HAS_ETH0
217 #define CONFIG_HAS_ETH1
218 #define CONFIG_HAS_ETH2
221 #define CONFIG_CMD_PING
222 #define CONFIG_CMD_DHCP
223 #define CONFIG_CMD_MII
224 #define CONFIG_CMD_NET
226 #define CONFIG_CMDLINE_TAG
227 #define CONFIG_CMDLINE_EDITING
228 #define CONFIG_CMD_IMLS
230 #define CONFIG_HWCONFIG
231 #define HWCONFIG_BUFFER_SIZE 128
233 #define CONFIG_BOOTDELAY 3
235 #define CONFIG_EXTRA_ENV_SETTINGS \
236 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
237 "initrd_high=0xcfffffff\0" \
238 "fdt_high=0xcfffffff\0"
241 * Miscellaneous configurable options
243 #define CONFIG_SYS_LONGHELP /* undef to save memory */
244 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
245 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
246 #define CONFIG_SYS_PROMPT "=> "
247 #define CONFIG_AUTO_COMPLETE
248 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
249 #define CONFIG_SYS_PBSIZE \
250 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
251 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
252 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
254 #define CONFIG_CMD_ENV_EXISTS
255 #define CONFIG_CMD_GREPENV
256 #define CONFIG_CMD_MEMINFO
257 #define CONFIG_CMD_MEMTEST
258 #define CONFIG_SYS_MEMTEST_START 0x80000000
259 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
261 #define CONFIG_SYS_LOAD_ADDR 0x82000000
262 #define CONFIG_SYS_HZ 1000
266 * The stack sizes are set up in start.S using the settings below
268 #define CONFIG_STACKSIZE (30 * 1024)
270 #define CONFIG_SYS_INIT_SP_OFFSET \
271 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
272 #define CONFIG_SYS_INIT_SP_ADDR \
273 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
280 #define CONFIG_ENV_OVERWRITE
282 #define CONFIG_ENV_IS_IN_FLASH
283 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
284 #define CONFIG_ENV_SIZE 0x20000
285 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
287 #define CONFIG_OF_LIBFDT
288 #define CONFIG_OF_BOARD_SETUP
289 #define CONFIG_CMD_BOOTZ