2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_ARMV7_PSCI_1_0
14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO
21 #define CONFIG_SKIP_LOWLEVEL_INIT
22 #define CONFIG_BOARD_EARLY_INIT_F
23 #define CONFIG_DEEP_SLEEP
24 #ifdef CONFIG_DEEP_SLEEP
25 #define CONFIG_SILENT_CONSOLE
29 * Size of malloc() pool
31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
41 * EHCI Support - disbaled by default as
42 * there is no signal coming out of soc on
43 * this board for this controller. However,
44 * the silicon still has this controller,
45 * and anyone can use this controller by
46 * taking signals out on their board.
49 /*#define CONFIG_HAS_FSL_DR_USB*/
51 #ifdef CONFIG_HAS_FSL_DR_USB
52 #define CONFIG_USB_EHCI
53 #define CONFIG_USB_EHCI_FSL
54 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
57 /* XHCI Support - enabled by default */
58 #define CONFIG_HAS_FSL_XHCI_USB
60 #ifdef CONFIG_HAS_FSL_XHCI_USB
61 #define CONFIG_USB_XHCI_FSL
62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
67 * Generic Timer Definitions
69 #define GENERIC_TIMER_CLK 12500000
71 #define CONFIG_SYS_CLK_FREQ 100000000
72 #define CONFIG_DDR_CLK_FREQ 100000000
74 #define DDR_SDRAM_CFG 0x470c0008
75 #define DDR_CS0_BNDS 0x008000bf
76 #define DDR_CS0_CONFIG 0x80014302
77 #define DDR_TIMING_CFG_0 0x50550004
78 #define DDR_TIMING_CFG_1 0xbcb38c56
79 #define DDR_TIMING_CFG_2 0x0040d120
80 #define DDR_TIMING_CFG_3 0x010e1000
81 #define DDR_TIMING_CFG_4 0x00000001
82 #define DDR_TIMING_CFG_5 0x03401400
83 #define DDR_SDRAM_CFG_2 0x00401010
84 #define DDR_SDRAM_MODE 0x00061c60
85 #define DDR_SDRAM_MODE_2 0x00180000
86 #define DDR_SDRAM_INTERVAL 0x18600618
87 #define DDR_DDR_WRLVL_CNTL 0x8655f605
88 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
89 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
90 #define DDR_DDR_CDR1 0x80040000
91 #define DDR_DDR_CDR2 0x00000001
92 #define DDR_SDRAM_CLK_CNTL 0x02000000
93 #define DDR_DDR_ZQ_CNTL 0x89080600
94 #define DDR_CS0_CONFIG_2 0
95 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
96 #define SDRAM_CFG2_D_INIT 0x00000010
97 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
98 #define SDRAM_CFG2_FRC_SR 0x80000000
99 #define SDRAM_CFG_BI 0x00000001
101 #ifdef CONFIG_RAMBOOT_PBL
102 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
105 #ifdef CONFIG_SD_BOOT
106 #ifdef CONFIG_SD_BOOT_QSPI
107 #define CONFIG_SYS_FSL_PBL_RCW \
108 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
110 #define CONFIG_SYS_FSL_PBL_RCW \
111 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
113 #define CONFIG_SPL_FRAMEWORK
114 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
115 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
116 #define CONFIG_SPL_WATCHDOG_SUPPORT
117 #define CONFIG_SPL_SERIAL_SUPPORT
118 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
120 #ifdef CONFIG_SECURE_BOOT
121 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
123 * HDR would be appended at end of image and copied to DDR along
126 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
127 (CONFIG_U_BOOT_HDR_SIZE / 512)
129 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
130 #endif /* ifdef CONFIG_SECURE_BOOT */
132 #define CONFIG_SPL_TEXT_BASE 0x10000000
133 #define CONFIG_SPL_MAX_SIZE 0x1a000
134 #define CONFIG_SPL_STACK 0x1001d000
135 #define CONFIG_SPL_PAD_TO 0x1c000
136 #define CONFIG_SYS_TEXT_BASE 0x82000000
138 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
139 CONFIG_SYS_MONITOR_LEN)
140 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
141 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
142 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
144 #ifdef CONFIG_U_BOOT_HDR_SIZE
146 * HDR would be appended at end of image and copied to DDR along
147 * with U-Boot image. Here u-boot max. size is 512K. So if binary
148 * size increases then increase this size in case of secure boot as
149 * it uses raw u-boot image instead of fit image.
151 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
153 #define CONFIG_SYS_MONITOR_LEN 0x80000
154 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
157 #ifdef CONFIG_QSPI_BOOT
158 #define CONFIG_SYS_TEXT_BASE 0x40010000
161 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
162 #define CONFIG_SYS_NO_FLASH
165 #ifndef CONFIG_SYS_TEXT_BASE
166 #define CONFIG_SYS_TEXT_BASE 0x60100000
169 #define CONFIG_NR_DRAM_BANKS 1
170 #define PHYS_SDRAM 0x80000000
171 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
173 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
174 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
176 #define CONFIG_SYS_HAS_SERDES
178 #define CONFIG_FSL_CAAM /* Enable CAAM */
180 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
181 !defined(CONFIG_QSPI_BOOT)
188 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
189 #define CONFIG_FSL_IFC
190 #define CONFIG_SYS_FLASH_BASE 0x60000000
191 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
193 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
194 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
195 CSPR_PORT_SIZE_16 | \
198 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
200 /* NOR Flash Timing Params */
201 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
203 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
204 FTIM0_NOR_TEADC(0x5) | \
205 FTIM0_NOR_TAVDS(0x0) | \
206 FTIM0_NOR_TEAHC(0x5))
207 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
208 FTIM1_NOR_TRAD_NOR(0x1A) | \
209 FTIM1_NOR_TSEQRAD_NOR(0x13))
210 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
211 FTIM2_NOR_TCH(0x4) | \
212 FTIM2_NOR_TWP(0x1c) | \
213 FTIM2_NOR_TWPH(0x0e))
214 #define CONFIG_SYS_NOR_FTIM3 0
216 #define CONFIG_FLASH_CFI_DRIVER
217 #define CONFIG_SYS_FLASH_CFI
218 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
219 #define CONFIG_SYS_FLASH_QUIET_TEST
220 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
223 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
224 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
225 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
227 #define CONFIG_SYS_FLASH_EMPTY_INFO
228 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
230 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
231 #define CONFIG_SYS_WRITE_SWAPPED_DATA
236 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
237 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
239 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
240 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
244 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
245 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
246 CSOR_NOR_NOR_MODE_AVD_NOR | \
249 /* CPLD Timing parameters for IFC GPCM */
250 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
251 FTIM0_GPCM_TEADC(0xf) | \
252 FTIM0_GPCM_TEAHC(0xf))
253 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
254 FTIM1_GPCM_TRAD(0x3f))
255 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
256 FTIM2_GPCM_TCH(0xf) | \
257 FTIM2_GPCM_TWP(0xff))
258 #define CONFIG_SYS_FPGA_FTIM3 0x0
259 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
260 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
261 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
262 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
263 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
264 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
265 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
266 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
267 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
268 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
269 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
270 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
271 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
272 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
273 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
274 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
280 #define CONFIG_LPUART_32B_REG
282 #define CONFIG_CONS_INDEX 1
283 #define CONFIG_SYS_NS16550_SERIAL
284 #ifndef CONFIG_DM_SERIAL
285 #define CONFIG_SYS_NS16550_REG_SIZE 1
287 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
290 #define CONFIG_BAUDRATE 115200
295 #define CONFIG_SYS_I2C
296 #define CONFIG_SYS_I2C_MXC
297 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
298 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
299 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
302 #define CONFIG_ID_EEPROM
303 #define CONFIG_SYS_I2C_EEPROM_NXID
304 #define CONFIG_SYS_EEPROM_BUS_NUM 1
305 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
306 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
307 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
308 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
314 #define CONFIG_FSL_ESDHC
315 #define CONFIG_GENERIC_MMC
317 #define CONFIG_DOS_PARTITION
320 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
322 #define QSPI0_AMBA_BASE 0x40000000
323 #define FSL_QSPI_FLASH_SIZE (1 << 24)
324 #define FSL_QSPI_FLASH_NUM 2
330 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
331 #define CONFIG_DM_SPI_FLASH
337 #define CONFIG_FSL_DCU_FB
339 #ifdef CONFIG_FSL_DCU_FB
341 #define CONFIG_CMD_BMP
342 #define CONFIG_CFB_CONSOLE
343 #define CONFIG_VGA_AS_SINGLE_DEVICE
344 #define CONFIG_VIDEO_LOGO
345 #define CONFIG_VIDEO_BMP_LOGO
346 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
348 #define CONFIG_FSL_DCU_SII9022A
349 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
350 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
356 #define CONFIG_TSEC_ENET
358 #ifdef CONFIG_TSEC_ENET
360 #define CONFIG_MII_DEFAULT_TSEC 1
361 #define CONFIG_TSEC1 1
362 #define CONFIG_TSEC1_NAME "eTSEC1"
363 #define CONFIG_TSEC2 1
364 #define CONFIG_TSEC2_NAME "eTSEC2"
365 #define CONFIG_TSEC3 1
366 #define CONFIG_TSEC3_NAME "eTSEC3"
368 #define TSEC1_PHY_ADDR 2
369 #define TSEC2_PHY_ADDR 0
370 #define TSEC3_PHY_ADDR 1
372 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
373 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
374 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
376 #define TSEC1_PHYIDX 0
377 #define TSEC2_PHYIDX 0
378 #define TSEC3_PHYIDX 0
380 #define CONFIG_ETHPRIME "eTSEC1"
382 #define CONFIG_PHY_GIGE
383 #define CONFIG_PHYLIB
384 #define CONFIG_PHY_ATHEROS
386 #define CONFIG_HAS_ETH0
387 #define CONFIG_HAS_ETH1
388 #define CONFIG_HAS_ETH2
392 #define CONFIG_PCI /* Enable PCI/PCIE */
393 #define CONFIG_PCIE1 /* PCIE controller 1 */
394 #define CONFIG_PCIE2 /* PCIE controller 2 */
395 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
396 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
398 #define CONFIG_SYS_PCI_64BIT
400 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
401 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
402 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
403 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
405 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
406 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
407 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
409 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
410 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
411 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
414 #define CONFIG_PCI_PNP
415 #define CONFIG_PCI_SCAN_SHOW
416 #define CONFIG_CMD_PCI
419 #define CONFIG_CMDLINE_TAG
420 #define CONFIG_CMDLINE_EDITING
422 #define CONFIG_ARMV7_NONSEC
423 #define CONFIG_ARMV7_VIRT
424 #define CONFIG_PEN_ADDR_BIG_ENDIAN
425 #define CONFIG_LAYERSCAPE_NS_ACCESS
426 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
427 #define CONFIG_TIMER_CLK_FREQ 12500000
429 #define CONFIG_HWCONFIG
430 #define HWCONFIG_BUFFER_SIZE 256
432 #define CONFIG_FSL_DEVICE_DISABLE
436 #define CONFIG_EXTRA_ENV_SETTINGS \
437 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
438 "initrd_high=0xffffffff\0" \
439 "fdt_high=0xffffffff\0"
441 #define CONFIG_EXTRA_ENV_SETTINGS \
442 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
443 "initrd_high=0xffffffff\0" \
444 "fdt_high=0xffffffff\0"
448 * Miscellaneous configurable options
450 #define CONFIG_SYS_LONGHELP /* undef to save memory */
451 #define CONFIG_AUTO_COMPLETE
452 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
453 #define CONFIG_SYS_PBSIZE \
454 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
455 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
456 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
458 #define CONFIG_SYS_MEMTEST_START 0x80000000
459 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
461 #define CONFIG_SYS_LOAD_ADDR 0x82000000
463 #define CONFIG_LS102XA_STREAM_ID
467 * The stack sizes are set up in start.S using the settings below
469 #define CONFIG_STACKSIZE (30 * 1024)
471 #define CONFIG_SYS_INIT_SP_OFFSET \
472 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
473 #define CONFIG_SYS_INIT_SP_ADDR \
474 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
476 #ifdef CONFIG_SPL_BUILD
477 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
479 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
482 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
487 #define CONFIG_ENV_OVERWRITE
489 #if defined(CONFIG_SD_BOOT)
490 #define CONFIG_ENV_OFFSET 0x100000
491 #define CONFIG_ENV_IS_IN_MMC
492 #define CONFIG_SYS_MMC_ENV_DEV 0
493 #define CONFIG_ENV_SIZE 0x20000
494 #elif defined(CONFIG_QSPI_BOOT)
495 #define CONFIG_ENV_IS_IN_SPI_FLASH
496 #define CONFIG_ENV_SIZE 0x2000
497 #define CONFIG_ENV_OFFSET 0x100000
498 #define CONFIG_ENV_SECT_SIZE 0x10000
500 #define CONFIG_ENV_IS_IN_FLASH
501 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
502 #define CONFIG_ENV_SIZE 0x20000
503 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
506 #define CONFIG_MISC_INIT_R
508 /* Hash command with SHA acceleration supported in hardware */
509 #ifdef CONFIG_FSL_CAAM
510 #define CONFIG_CMD_HASH
511 #define CONFIG_SHA_HW_ACCEL
514 #include <asm/fsl_secure_boot.h>
515 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */