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[u-boot] / include / configs / ls1021atwr.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5
6 #ifndef __CONFIG_H
7 #define __CONFIG_H
8
9 #define CONFIG_ARMV7_PSCI_1_0
10
11 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
12
13 #define CONFIG_SYS_FSL_CLK
14
15 #define CONFIG_SKIP_LOWLEVEL_INIT
16 #define CONFIG_DEEP_SLEEP
17
18 /*
19  * Size of malloc() pool
20  */
21 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
22
23 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
24 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
25
26 #define CONFIG_SYS_CLK_FREQ             100000000
27 #define CONFIG_DDR_CLK_FREQ             100000000
28
29 #define DDR_SDRAM_CFG                   0x470c0008
30 #define DDR_CS0_BNDS                    0x008000bf
31 #define DDR_CS0_CONFIG                  0x80014302
32 #define DDR_TIMING_CFG_0                0x50550004
33 #define DDR_TIMING_CFG_1                0xbcb38c56
34 #define DDR_TIMING_CFG_2                0x0040d120
35 #define DDR_TIMING_CFG_3                0x010e1000
36 #define DDR_TIMING_CFG_4                0x00000001
37 #define DDR_TIMING_CFG_5                0x03401400
38 #define DDR_SDRAM_CFG_2                 0x00401010
39 #define DDR_SDRAM_MODE                  0x00061c60
40 #define DDR_SDRAM_MODE_2                0x00180000
41 #define DDR_SDRAM_INTERVAL              0x18600618
42 #define DDR_DDR_WRLVL_CNTL              0x8655f605
43 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
44 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
45 #define DDR_DDR_CDR1                    0x80040000
46 #define DDR_DDR_CDR2                    0x00000001
47 #define DDR_SDRAM_CLK_CNTL              0x02000000
48 #define DDR_DDR_ZQ_CNTL                 0x89080600
49 #define DDR_CS0_CONFIG_2                0
50 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
51 #define SDRAM_CFG2_D_INIT               0x00000010
52 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
53 #define SDRAM_CFG2_FRC_SR               0x80000000
54 #define SDRAM_CFG_BI                    0x00000001
55
56 #ifdef CONFIG_RAMBOOT_PBL
57 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
58 #endif
59
60 #ifdef CONFIG_SD_BOOT
61 #ifdef CONFIG_SD_BOOT_QSPI
62 #define CONFIG_SYS_FSL_PBL_RCW  \
63         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
64 #else
65 #define CONFIG_SYS_FSL_PBL_RCW  \
66         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
67 #endif
68
69 #ifdef CONFIG_SECURE_BOOT
70 /*
71  * HDR would be appended at end of image and copied to DDR along
72  * with U-Boot image.
73  */
74 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
75 #endif /* ifdef CONFIG_SECURE_BOOT */
76
77 #define CONFIG_SPL_TEXT_BASE            0x10000000
78 #define CONFIG_SPL_MAX_SIZE             0x1a000
79 #define CONFIG_SPL_STACK                0x1001d000
80 #define CONFIG_SPL_PAD_TO               0x1c000
81
82 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
83                 CONFIG_SYS_MONITOR_LEN)
84 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
85 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
86 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
87
88 #ifdef CONFIG_U_BOOT_HDR_SIZE
89 /*
90  * HDR would be appended at end of image and copied to DDR along
91  * with U-Boot image. Here u-boot max. size is 512K. So if binary
92  * size increases then increase this size in case of secure boot as
93  * it uses raw u-boot image instead of fit image.
94  */
95 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
96 #else
97 #define CONFIG_SYS_MONITOR_LEN          0x100000
98 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
99 #endif
100
101 #define CONFIG_NR_DRAM_BANKS            1
102 #define PHYS_SDRAM                      0x80000000
103 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
104
105 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
106 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
107
108 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
109         !defined(CONFIG_QSPI_BOOT)
110 #define CONFIG_U_QE
111 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
112 #endif
113
114 /*
115  * IFC Definitions
116  */
117 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
118 #define CONFIG_FSL_IFC
119 #define CONFIG_SYS_FLASH_BASE           0x60000000
120 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
121
122 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
123 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
124                                 CSPR_PORT_SIZE_16 | \
125                                 CSPR_MSEL_NOR | \
126                                 CSPR_V)
127 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
128
129 /* NOR Flash Timing Params */
130 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
131                                         CSOR_NOR_TRHZ_80)
132 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
133                                         FTIM0_NOR_TEADC(0x5) | \
134                                         FTIM0_NOR_TAVDS(0x0) | \
135                                         FTIM0_NOR_TEAHC(0x5))
136 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
137                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
138                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
139 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
140                                         FTIM2_NOR_TCH(0x4) | \
141                                         FTIM2_NOR_TWP(0x1c) | \
142                                         FTIM2_NOR_TWPH(0x0e))
143 #define CONFIG_SYS_NOR_FTIM3            0
144
145 #define CONFIG_FLASH_CFI_DRIVER
146 #define CONFIG_SYS_FLASH_CFI
147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
148 #define CONFIG_SYS_FLASH_QUIET_TEST
149 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
150
151 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
153 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
154 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
155
156 #define CONFIG_SYS_FLASH_EMPTY_INFO
157 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
158
159 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
160 #define CONFIG_SYS_WRITE_SWAPPED_DATA
161 #endif
162
163 /* CPLD */
164
165 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
166 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
167
168 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
169 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
170                                         CSPR_PORT_SIZE_8 | \
171                                         CSPR_MSEL_GPCM | \
172                                         CSPR_V)
173 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
174 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
175                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
176                                         CSOR_NOR_TRHZ_80)
177
178 /* CPLD Timing parameters for IFC GPCM */
179 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
180                                         FTIM0_GPCM_TEADC(0xf) | \
181                                         FTIM0_GPCM_TEAHC(0xf))
182 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
183                                         FTIM1_GPCM_TRAD(0x3f))
184 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
185                                         FTIM2_GPCM_TCH(0xf) | \
186                                         FTIM2_GPCM_TWP(0xff))
187 #define CONFIG_SYS_FPGA_FTIM3           0x0
188 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
189 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
190 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
196 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
197 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
198 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
199 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
200 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
201 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
202 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
203 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
204
205 /*
206  * Serial Port
207  */
208 #ifdef CONFIG_LPUART
209 #define CONFIG_LPUART_32B_REG
210 #else
211 #define CONFIG_SYS_NS16550_SERIAL
212 #ifndef CONFIG_DM_SERIAL
213 #define CONFIG_SYS_NS16550_REG_SIZE     1
214 #endif
215 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
216 #endif
217
218 /*
219  * I2C
220  */
221 #define CONFIG_SYS_I2C
222 #define CONFIG_SYS_I2C_MXC
223 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
224 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
225 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
226
227 /* EEPROM */
228 #define CONFIG_ID_EEPROM
229 #define CONFIG_SYS_I2C_EEPROM_NXID
230 #define CONFIG_SYS_EEPROM_BUS_NUM               1
231 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
235
236 /*
237  * MMC
238  */
239
240 /* SPI */
241 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
242 /* QSPI */
243 #define QSPI0_AMBA_BASE                 0x40000000
244 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
245 #define FSL_QSPI_FLASH_NUM              2
246
247 /* DSPI */
248 #endif
249
250 /* DM SPI */
251 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
252 #define CONFIG_DM_SPI_FLASH
253 #endif
254
255 /*
256  * Video
257  */
258 #ifdef CONFIG_VIDEO_FSL_DCU_FB
259 #define CONFIG_VIDEO_LOGO
260 #define CONFIG_VIDEO_BMP_LOGO
261
262 #define CONFIG_FSL_DCU_SII9022A
263 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
264 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
265 #endif
266
267 /*
268  * eTSEC
269  */
270
271 #ifdef CONFIG_TSEC_ENET
272 #define CONFIG_MII
273 #define CONFIG_MII_DEFAULT_TSEC         1
274 #define CONFIG_TSEC1                    1
275 #define CONFIG_TSEC1_NAME               "eTSEC1"
276 #define CONFIG_TSEC2                    1
277 #define CONFIG_TSEC2_NAME               "eTSEC2"
278 #define CONFIG_TSEC3                    1
279 #define CONFIG_TSEC3_NAME               "eTSEC3"
280
281 #define TSEC1_PHY_ADDR                  2
282 #define TSEC2_PHY_ADDR                  0
283 #define TSEC3_PHY_ADDR                  1
284
285 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
286 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
287 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
288
289 #define TSEC1_PHYIDX                    0
290 #define TSEC2_PHYIDX                    0
291 #define TSEC3_PHYIDX                    0
292
293 #define CONFIG_ETHPRIME                 "eTSEC1"
294
295 #define CONFIG_PHY_ATHEROS
296
297 #define CONFIG_HAS_ETH0
298 #define CONFIG_HAS_ETH1
299 #define CONFIG_HAS_ETH2
300 #endif
301
302 /* PCIe */
303 #define CONFIG_PCIE1            /* PCIE controller 1 */
304 #define CONFIG_PCIE2            /* PCIE controller 2 */
305
306 #ifdef CONFIG_PCI
307 #define CONFIG_PCI_SCAN_SHOW
308 #endif
309
310 #define CONFIG_CMDLINE_TAG
311
312 #define CONFIG_PEN_ADDR_BIG_ENDIAN
313 #define CONFIG_LAYERSCAPE_NS_ACCESS
314 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
315 #define COUNTER_FREQUENCY               12500000
316
317 #define CONFIG_HWCONFIG
318 #define HWCONFIG_BUFFER_SIZE            256
319
320 #define CONFIG_FSL_DEVICE_DISABLE
321
322 #define BOOT_TARGET_DEVICES(func) \
323         func(MMC, mmc, 0) \
324         func(USB, usb, 0)
325 #include <config_distro_bootcmd.h>
326
327 #ifdef CONFIG_LPUART
328 #define CONFIG_EXTRA_ENV_SETTINGS       \
329         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
330         "initrd_high=0xffffffff\0"      \
331         "fdt_high=0xffffffff\0"         \
332         "fdt_addr=0x64f00000\0"         \
333         "kernel_addr=0x65000000\0"      \
334         "scriptaddr=0x80000000\0"       \
335         "scripthdraddr=0x80080000\0"    \
336         "fdtheader_addr_r=0x80100000\0" \
337         "kernelheader_addr_r=0x80200000\0"      \
338         "kernel_addr_r=0x81000000\0"    \
339         "fdt_addr_r=0x90000000\0"       \
340         "ramdisk_addr_r=0xa0000000\0"   \
341         "load_addr=0xa0000000\0"        \
342         "kernel_size=0x2800000\0"       \
343         "kernel_addr_sd=0x8000\0"       \
344         "kernel_size_sd=0x14000\0"      \
345         BOOTENV                         \
346         "boot_scripts=ls1021atwr_boot.scr\0"    \
347         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
348                 "scan_dev_for_boot_part="       \
349                         "part list ${devtype} ${devnum} devplist; "     \
350                         "env exists devplist || setenv devplist 1; "    \
351                         "for distro_bootpart in ${devplist}; do "       \
352                         "if fstype ${devtype} "                         \
353                                 "${devnum}:${distro_bootpart} "         \
354                                 "bootfstype; then "                     \
355                                 "run scan_dev_for_boot; "               \
356                         "fi; "                  \
357                 "done\0"                        \
358         "scan_dev_for_boot="                              \
359                 "echo Scanning ${devtype} "               \
360                                 "${devnum}:${distro_bootpart}...; "  \
361                 "for prefix in ${boot_prefixes}; do "     \
362                         "run scan_dev_for_scripts; "      \
363                 "done;"                                   \
364                 "\0"                                      \
365         "boot_a_script="                                  \
366                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
367                         "${scriptaddr} ${prefix}${script}; "    \
368                 "env exists secureboot && load ${devtype} "     \
369                         "${devnum}:${distro_bootpart} "         \
370                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
371                         "&& esbc_validate ${scripthdraddr};"    \
372                 "source ${scriptaddr}\0"          \
373         "installer=load mmc 0:2 $load_addr "    \
374                 "/flex_installer_arm32.itb; "           \
375                 "bootm $load_addr#ls1021atwr\0" \
376         "qspi_bootcmd=echo Trying load from qspi..;"    \
377                 "sf probe && sf read $load_addr "       \
378                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
379         "nor_bootcmd=echo Trying load from nor..;"      \
380                 "cp.b $kernel_addr $load_addr "         \
381                 "$kernel_size && bootm $load_addr#$board\0"
382 #else
383 #define CONFIG_EXTRA_ENV_SETTINGS       \
384         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
385         "initrd_high=0xffffffff\0"      \
386         "fdt_high=0xffffffff\0"         \
387         "fdt_addr=0x64f00000\0"         \
388         "kernel_addr=0x61000000\0"      \
389         "kernelheader_addr=0x60800000\0"        \
390         "scriptaddr=0x80000000\0"       \
391         "scripthdraddr=0x80080000\0"    \
392         "fdtheader_addr_r=0x80100000\0" \
393         "kernelheader_addr_r=0x80200000\0"      \
394         "kernel_addr_r=0x81000000\0"    \
395         "kernelheader_size=0x40000\0"   \
396         "fdt_addr_r=0x90000000\0"       \
397         "ramdisk_addr_r=0xa0000000\0"   \
398         "load_addr=0xa0000000\0"        \
399         "kernel_size=0x2800000\0"       \
400         "kernel_addr_sd=0x8000\0"       \
401         "kernel_size_sd=0x14000\0"      \
402         "kernelhdr_addr_sd=0x4000\0"            \
403         "kernelhdr_size_sd=0x10\0"              \
404         BOOTENV                         \
405         "boot_scripts=ls1021atwr_boot.scr\0"    \
406         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
407                 "scan_dev_for_boot_part="       \
408                         "part list ${devtype} ${devnum} devplist; "     \
409                         "env exists devplist || setenv devplist 1; "    \
410                         "for distro_bootpart in ${devplist}; do "       \
411                         "if fstype ${devtype} "                         \
412                                 "${devnum}:${distro_bootpart} "         \
413                                 "bootfstype; then "                     \
414                                 "run scan_dev_for_boot; "               \
415                         "fi; "                  \
416                 "done\0"                        \
417         "scan_dev_for_boot="                              \
418                 "echo Scanning ${devtype} "               \
419                                 "${devnum}:${distro_bootpart}...; "  \
420                 "for prefix in ${boot_prefixes}; do "     \
421                         "run scan_dev_for_scripts; "      \
422                 "done;"                                   \
423                 "\0"                                      \
424         "boot_a_script="                                  \
425                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
426                         "${scriptaddr} ${prefix}${script}; "    \
427                 "env exists secureboot && load ${devtype} "     \
428                         "${devnum}:${distro_bootpart} "         \
429                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
430                         "&& esbc_validate ${scripthdraddr};"    \
431                 "source ${scriptaddr}\0"          \
432         "qspi_bootcmd=echo Trying load from qspi..;"    \
433                 "sf probe && sf read $load_addr "       \
434                 "$kernel_addr $kernel_size; env exists secureboot "     \
435                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
436                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
437                 "bootm $load_addr#$board\0" \
438         "nor_bootcmd=echo Trying load from nor..;"      \
439                 "cp.b $kernel_addr $load_addr "         \
440                 "$kernel_size; env exists secureboot "  \
441                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
442                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
443                 "bootm $load_addr#$board\0"     \
444         "sd_bootcmd=echo Trying load from SD ..;"       \
445                 "mmcinfo && mmc read $load_addr "       \
446                 "$kernel_addr_sd $kernel_size_sd && "   \
447                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
448                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
449                 " && esbc_validate ${kernelheader_addr_r};"     \
450                 "bootm $load_addr#$board\0"
451 #endif
452
453 #undef CONFIG_BOOTCOMMAND
454 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
455 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd"       \
456                            "env exists secureboot && esbc_halt"
457 #elif defined(CONFIG_SD_BOOT)
458 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
459                            "env exists secureboot && esbc_halt;"
460 #else
461 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"       \
462                            "env exists secureboot && esbc_halt;"
463 #endif
464
465 /*
466  * Miscellaneous configurable options
467  */
468
469 #define CONFIG_SYS_MEMTEST_START        0x80000000
470 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
471
472 #define CONFIG_SYS_LOAD_ADDR            0x82000000
473
474 #define CONFIG_LS102XA_STREAM_ID
475
476 #define CONFIG_SYS_INIT_SP_OFFSET \
477         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
478 #define CONFIG_SYS_INIT_SP_ADDR \
479         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
480
481 #ifdef CONFIG_SPL_BUILD
482 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
483 #else
484 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
485 #endif
486
487 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
488
489 /*
490  * Environment
491  */
492 #define CONFIG_ENV_OVERWRITE
493
494 #if defined(CONFIG_SD_BOOT)
495 #define CONFIG_ENV_OFFSET               0x300000
496 #define CONFIG_SYS_MMC_ENV_DEV          0
497 #define CONFIG_ENV_SIZE                 0x20000
498 #elif defined(CONFIG_QSPI_BOOT)
499 #define CONFIG_ENV_SIZE                 0x2000
500 #define CONFIG_ENV_OFFSET               0x300000
501 #define CONFIG_ENV_SECT_SIZE            0x10000
502 #else
503 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
504 #define CONFIG_ENV_SIZE                 0x20000
505 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
506 #endif
507
508 #define CONFIG_MISC_INIT_R
509
510 #include <asm/fsl_secure_boot.h>
511 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
512
513 #endif