git.sur5r.net Git - u-boot/blob - include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_PSCI_1_0
  11
  12 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17 #define CONFIG_DEEP_SLEEP
  18
  19 /*
  20  * Size of malloc() pool
  21  */
  22 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  23
  24 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  25 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  26
  27 /*
  28  * USB
  29  */
  30
  31 /*
  32  * EHCI Support - disbaled by default as
  33  * there is no signal coming out of soc on
  34  * this board for this controller. However,
  35  * the silicon still has this controller,
  36  * and anyone can use this controller by
  37  * taking signals out on their board.
  38  */
  39
  40 /*#define CONFIG_HAS_FSL_DR_USB*/
  41
  42 #ifdef CONFIG_HAS_FSL_DR_USB
  43 #define CONFIG_USB_EHCI_FSL
  44 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  45 #endif
  46
  47 /* XHCI Support - enabled by default */
  48 #define CONFIG_USB_XHCI_FSL
  49 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
  50
  51 #define CONFIG_SYS_CLK_FREQ             100000000
  52 #define CONFIG_DDR_CLK_FREQ             100000000
  53
  54 #define DDR_SDRAM_CFG                   0x470c0008
  55 #define DDR_CS0_BNDS                    0x008000bf
  56 #define DDR_CS0_CONFIG                  0x80014302
  57 #define DDR_TIMING_CFG_0                0x50550004
  58 #define DDR_TIMING_CFG_1                0xbcb38c56
  59 #define DDR_TIMING_CFG_2                0x0040d120
  60 #define DDR_TIMING_CFG_3                0x010e1000
  61 #define DDR_TIMING_CFG_4                0x00000001
  62 #define DDR_TIMING_CFG_5                0x03401400
  63 #define DDR_SDRAM_CFG_2                 0x00401010
  64 #define DDR_SDRAM_MODE                  0x00061c60
  65 #define DDR_SDRAM_MODE_2                0x00180000
  66 #define DDR_SDRAM_INTERVAL              0x18600618
  67 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  68 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  69 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  70 #define DDR_DDR_CDR1                    0x80040000
  71 #define DDR_DDR_CDR2                    0x00000001
  72 #define DDR_SDRAM_CLK_CNTL              0x02000000
  73 #define DDR_DDR_ZQ_CNTL                 0x89080600
  74 #define DDR_CS0_CONFIG_2                0
  75 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  76 #define SDRAM_CFG2_D_INIT               0x00000010
  77 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  78 #define SDRAM_CFG2_FRC_SR               0x80000000
  79 #define SDRAM_CFG_BI                    0x00000001
  80
  81 #ifdef CONFIG_RAMBOOT_PBL
  82 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  83 #endif
  84
  85 #ifdef CONFIG_SD_BOOT
  86 #ifdef CONFIG_SD_BOOT_QSPI
  87 #define CONFIG_SYS_FSL_PBL_RCW  \
  88         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  89 #else
  90 #define CONFIG_SYS_FSL_PBL_RCW  \
  91         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  92 #endif
  93 #define CONFIG_SPL_FRAMEWORK
  94
  95 #ifdef CONFIG_SECURE_BOOT
  96 /*
  97  * HDR would be appended at end of image and copied to DDR along
  98  * with U-Boot image.
  99  */
 100 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 101 #endif /* ifdef CONFIG_SECURE_BOOT */
 102
 103 #define CONFIG_SPL_TEXT_BASE            0x10000000
 104 #define CONFIG_SPL_MAX_SIZE             0x1a000
 105 #define CONFIG_SPL_STACK                0x1001d000
 106 #define CONFIG_SPL_PAD_TO               0x1c000
 107 #define CONFIG_SYS_TEXT_BASE            0x82000000
 108
 109 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 110                 CONFIG_SYS_MONITOR_LEN)
 111 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 112 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 113 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 114
 115 #ifdef CONFIG_U_BOOT_HDR_SIZE
 116 /*
 117  * HDR would be appended at end of image and copied to DDR along
 118  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 119  * size increases then increase this size in case of secure boot as
 120  * it uses raw u-boot image instead of fit image.
 121  */
 122 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 123 #else
 124 #define CONFIG_SYS_MONITOR_LEN          0x100000
 125 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 126 #endif
 127
 128 #ifdef CONFIG_QSPI_BOOT
 129 #define CONFIG_SYS_TEXT_BASE            0x40100000
 130 #endif
 131
 132 #ifndef CONFIG_SYS_TEXT_BASE
 133 #define CONFIG_SYS_TEXT_BASE            0x60100000
 134 #endif
 135
 136 #define CONFIG_NR_DRAM_BANKS            1
 137 #define PHYS_SDRAM                      0x80000000
 138 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 139
 140 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 141 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 142
 143 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 144         !defined(CONFIG_QSPI_BOOT)
 145 #define CONFIG_U_QE
 146 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 147 #endif
 148
 149 /*
 150  * IFC Definitions
 151  */
 152 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 153 #define CONFIG_FSL_IFC
 154 #define CONFIG_SYS_FLASH_BASE           0x60000000
 155 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 156
 157 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 158 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 159                                 CSPR_PORT_SIZE_16 | \
 160                                 CSPR_MSEL_NOR | \
 161                                 CSPR_V)
 162 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 163
 164 /* NOR Flash Timing Params */
 165 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 166                                         CSOR_NOR_TRHZ_80)
 167 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 168                                         FTIM0_NOR_TEADC(0x5) | \
 169                                         FTIM0_NOR_TAVDS(0x0) | \
 170                                         FTIM0_NOR_TEAHC(0x5))
 171 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 172                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 173                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 174 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 175                                         FTIM2_NOR_TCH(0x4) | \
 176                                         FTIM2_NOR_TWP(0x1c) | \
 177                                         FTIM2_NOR_TWPH(0x0e))
 178 #define CONFIG_SYS_NOR_FTIM3            0
 179
 180 #define CONFIG_FLASH_CFI_DRIVER
 181 #define CONFIG_SYS_FLASH_CFI
 182 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 183 #define CONFIG_SYS_FLASH_QUIET_TEST
 184 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 185
 186 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 187 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 188 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 189 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 190
 191 #define CONFIG_SYS_FLASH_EMPTY_INFO
 192 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 193
 194 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 195 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 196 #endif
 197
 198 /* CPLD */
 199
 200 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 201 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 202
 203 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 204 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 205                                         CSPR_PORT_SIZE_8 | \
 206                                         CSPR_MSEL_GPCM | \
 207                                         CSPR_V)
 208 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 209 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 210                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 211                                         CSOR_NOR_TRHZ_80)
 212
 213 /* CPLD Timing parameters for IFC GPCM */
 214 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 215                                         FTIM0_GPCM_TEADC(0xf) | \
 216                                         FTIM0_GPCM_TEAHC(0xf))
 217 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 218                                         FTIM1_GPCM_TRAD(0x3f))
 219 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 220                                         FTIM2_GPCM_TCH(0xf) | \
 221                                         FTIM2_GPCM_TWP(0xff))
 222 #define CONFIG_SYS_FPGA_FTIM3           0x0
 223 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 224 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 225 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 226 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 227 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 228 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 229 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 230 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 231 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 232 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 233 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 234 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 235 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 236 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 237 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 238 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 239
 240 /*
 241  * Serial Port
 242  */
 243 #ifdef CONFIG_LPUART
 244 #define CONFIG_LPUART_32B_REG
 245 #else
 246 #define CONFIG_CONS_INDEX               1
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #ifndef CONFIG_DM_SERIAL
 249 #define CONFIG_SYS_NS16550_REG_SIZE     1
 250 #endif
 251 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 252 #endif
 253
 254 /*
 255  * I2C
 256  */
 257 #define CONFIG_SYS_I2C
 258 #define CONFIG_SYS_I2C_MXC
 259 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 260 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 261 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 262
 263 /* EEPROM */
 264 #define CONFIG_ID_EEPROM
 265 #define CONFIG_SYS_I2C_EEPROM_NXID
 266 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 267 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 268 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 270 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 271
 272 /*
 273  * MMC
 274  */
 275 #define CONFIG_FSL_ESDHC
 276
 277 /* SPI */
 278 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 279 /* QSPI */
 280 #define QSPI0_AMBA_BASE                 0x40000000
 281 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 282 #define FSL_QSPI_FLASH_NUM              2
 283
 284 /* DSPI */
 285 #endif
 286
 287 /* DM SPI */
 288 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 289 #define CONFIG_DM_SPI_FLASH
 290 #endif
 291
 292 /*
 293  * Video
 294  */
 295 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 296 #define CONFIG_VIDEO_LOGO
 297 #define CONFIG_VIDEO_BMP_LOGO
 298
 299 #define CONFIG_FSL_DCU_SII9022A
 300 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 301 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 302 #endif
 303
 304 /*
 305  * eTSEC
 306  */
 307 #define CONFIG_TSEC_ENET
 308
 309 #ifdef CONFIG_TSEC_ENET
 310 #define CONFIG_MII
 311 #define CONFIG_MII_DEFAULT_TSEC         1
 312 #define CONFIG_TSEC1                    1
 313 #define CONFIG_TSEC1_NAME               "eTSEC1"
 314 #define CONFIG_TSEC2                    1
 315 #define CONFIG_TSEC2_NAME               "eTSEC2"
 316 #define CONFIG_TSEC3                    1
 317 #define CONFIG_TSEC3_NAME               "eTSEC3"
 318
 319 #define TSEC1_PHY_ADDR                  2
 320 #define TSEC2_PHY_ADDR                  0
 321 #define TSEC3_PHY_ADDR                  1
 322
 323 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 324 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 325 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 326
 327 #define TSEC1_PHYIDX                    0
 328 #define TSEC2_PHYIDX                    0
 329 #define TSEC3_PHYIDX                    0
 330
 331 #define CONFIG_ETHPRIME                 "eTSEC1"
 332
 333 #define CONFIG_PHY_ATHEROS
 334
 335 #define CONFIG_HAS_ETH0
 336 #define CONFIG_HAS_ETH1
 337 #define CONFIG_HAS_ETH2
 338 #endif
 339
 340 /* PCIe */
 341 #define CONFIG_PCIE1            /* PCIE controller 1 */
 342 #define CONFIG_PCIE2            /* PCIE controller 2 */
 343
 344 #ifdef CONFIG_PCI
 345 #define CONFIG_PCI_SCAN_SHOW
 346 #endif
 347
 348 #define CONFIG_CMDLINE_TAG
 349
 350 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 351 #define CONFIG_LAYERSCAPE_NS_ACCESS
 352 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 353 #define COUNTER_FREQUENCY               12500000
 354
 355 #define CONFIG_HWCONFIG
 356 #define HWCONFIG_BUFFER_SIZE            256
 357
 358 #define CONFIG_FSL_DEVICE_DISABLE
 359
 360 #include <config_distro_defaults.h>
 361 #define BOOT_TARGET_DEVICES(func) \
 362         func(MMC, mmc, 0) \
 363         func(USB, usb, 0)
 364 #include <config_distro_bootcmd.h>
 365
 366 #ifdef CONFIG_LPUART
 367 #define CONFIG_EXTRA_ENV_SETTINGS       \
 368         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 369         "initrd_high=0xffffffff\0"      \
 370         "fdt_high=0xffffffff\0"         \
 371         "fdt_addr=0x64f00000\0"         \
 372         "kernel_addr=0x65000000\0"      \
 373         "scriptaddr=0x80000000\0"       \
 374         "scripthdraddr=0x80080000\0"    \
 375         "fdtheader_addr_r=0x80100000\0" \
 376         "kernelheader_addr_r=0x80200000\0"      \
 377         "kernel_addr_r=0x81000000\0"    \
 378         "fdt_addr_r=0x90000000\0"       \
 379         "ramdisk_addr_r=0xa0000000\0"   \
 380         "load_addr=0xa0000000\0"        \
 381         "kernel_size=0x2800000\0"       \
 382         BOOTENV                         \
 383         "boot_scripts=ls1021atwr_boot.scr\0"    \
 384         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 385                 "scan_dev_for_boot_part="       \
 386                         "part list ${devtype} ${devnum} devplist; "     \
 387                         "env exists devplist || setenv devplist 1; "    \
 388                         "for distro_bootpart in ${devplist}; do "       \
 389                         "if fstype ${devtype} "                         \
 390                                 "${devnum}:${distro_bootpart} "         \
 391                                 "bootfstype; then "                     \
 392                                 "run scan_dev_for_boot; "               \
 393                         "fi; "                  \
 394                 "done\0"                        \
 395         "scan_dev_for_boot="                              \
 396                 "echo Scanning ${devtype} "               \
 397                                 "${devnum}:${distro_bootpart}...; "  \
 398                 "for prefix in ${boot_prefixes}; do "     \
 399                         "run scan_dev_for_scripts; "      \
 400                 "done;"                                   \
 401                 "\0"                                      \
 402         "boot_a_script="                                  \
 403                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 404                         "${scriptaddr} ${prefix}${script}; "    \
 405                 "env exists secureboot && load ${devtype} "     \
 406                         "${devnum}:${distro_bootpart} "         \
 407                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 408                         "&& esbc_validate ${scripthdraddr};"    \
 409                 "source ${scriptaddr}\0"          \
 410         "installer=load mmc 0:2 $load_addr "    \
 411                 "/flex_installer_arm32.itb; "           \
 412                 "bootm $load_addr#ls1021atwr\0" \
 413         "qspi_bootcmd=echo Trying load from qspi..;"    \
 414                 "sf probe && sf read $load_addr "       \
 415                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 416         "nor_bootcmd=echo Trying load from nor..;"      \
 417                 "cp.b $kernel_addr $load_addr "         \
 418                 "$kernel_size && bootm $load_addr#$board\0"
 419 #else
 420 #define CONFIG_EXTRA_ENV_SETTINGS       \
 421         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 422         "initrd_high=0xffffffff\0"      \
 423         "fdt_high=0xffffffff\0"         \
 424         "fdt_addr=0x64f00000\0"         \
 425         "kernel_addr=0x65000000\0"      \
 426         "scriptaddr=0x80000000\0"       \
 427         "scripthdraddr=0x80080000\0"    \
 428         "fdtheader_addr_r=0x80100000\0" \
 429         "kernelheader_addr_r=0x80200000\0"      \
 430         "kernel_addr_r=0x81000000\0"    \
 431         "fdt_addr_r=0x90000000\0"       \
 432         "ramdisk_addr_r=0xa0000000\0"   \
 433         "load_addr=0xa0000000\0"        \
 434         "kernel_size=0x2800000\0"       \
 435         BOOTENV                         \
 436         "boot_scripts=ls1021atwr_boot.scr\0"    \
 437         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 438                 "scan_dev_for_boot_part="       \
 439                         "part list ${devtype} ${devnum} devplist; "     \
 440                         "env exists devplist || setenv devplist 1; "    \
 441                         "for distro_bootpart in ${devplist}; do "       \
 442                         "if fstype ${devtype} "                         \
 443                                 "${devnum}:${distro_bootpart} "         \
 444                                 "bootfstype; then "                     \
 445                                 "run scan_dev_for_boot; "               \
 446                         "fi; "                  \
 447                 "done\0"                        \
 448         "scan_dev_for_boot="                              \
 449                 "echo Scanning ${devtype} "               \
 450                                 "${devnum}:${distro_bootpart}...; "  \
 451                 "for prefix in ${boot_prefixes}; do "     \
 452                         "run scan_dev_for_scripts; "      \
 453                 "done;"                                   \
 454                 "\0"                                      \
 455         "boot_a_script="                                  \
 456                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 457                         "${scriptaddr} ${prefix}${script}; "    \
 458                 "env exists secureboot && load ${devtype} "     \
 459                         "${devnum}:${distro_bootpart} "         \
 460                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 461                         "&& esbc_validate ${scripthdraddr};"    \
 462                 "source ${scriptaddr}\0"          \
 463         "installer=load mmc 0:2 $load_addr "    \
 464                 "/flex_installer_arm32.itb; "           \
 465                 "bootm $load_addr#ls1021atwr\0" \
 466         "qspi_bootcmd=echo Trying load from qspi..;"    \
 467                 "sf probe && sf read $load_addr "       \
 468                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 469         "nor_bootcmd=echo Trying load from nor..;"      \
 470                 "cp.b $kernel_addr $load_addr "         \
 471                 "$kernel_size && bootm $load_addr#$board\0"
 472 #endif
 473
 474 #undef CONFIG_BOOTCOMMAND
 475 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 476 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"  \
 477                            "&& esbc_halt; run qspi_bootcmd;"
 478 #else
 479 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"  \
 480                            "&& esbc_halt; run nor_bootcmd;"
 481 #endif
 482
 483 /*
 484  * Miscellaneous configurable options
 485  */
 486 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 487 #define CONFIG_AUTO_COMPLETE
 488
 489 #define CONFIG_SYS_MEMTEST_START        0x80000000
 490 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 491
 492 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 493
 494 #define CONFIG_LS102XA_STREAM_ID
 495
 496 #define CONFIG_SYS_INIT_SP_OFFSET \
 497         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 498 #define CONFIG_SYS_INIT_SP_ADDR \
 499         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 500
 501 #ifdef CONFIG_SPL_BUILD
 502 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 503 #else
 504 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 505 #endif
 506
 507 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 508
 509 /*
 510  * Environment
 511  */
 512 #define CONFIG_ENV_OVERWRITE
 513
 514 #if defined(CONFIG_SD_BOOT)
 515 #define CONFIG_ENV_OFFSET               0x300000
 516 #define CONFIG_SYS_MMC_ENV_DEV          0
 517 #define CONFIG_ENV_SIZE                 0x20000
 518 #elif defined(CONFIG_QSPI_BOOT)
 519 #define CONFIG_ENV_SIZE                 0x2000
 520 #define CONFIG_ENV_OFFSET               0x300000
 521 #define CONFIG_ENV_SECT_SIZE            0x10000
 522 #else
 523 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 524 #define CONFIG_ENV_SIZE                 0x20000
 525 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 526 #endif
 527
 528 #define CONFIG_MISC_INIT_R
 529
 530 #include <asm/fsl_secure_boot.h>
 531 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 532
 533 #endif