git.sur5r.net Git - u-boot/blob - include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI
  13
  14 #define CONFIG_SYS_GENERIC_BOARD
  15
  16 #define CONFIG_DISPLAY_CPUINFO
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20 #define CONFIG_BOARD_EARLY_INIT_F
  21
  22 /*
  23  * Size of malloc() pool
  24  */
  25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  26
  27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  29
  30 /*
  31  * Generic Timer Definitions
  32  */
  33 #define GENERIC_TIMER_CLK               12500000
  34
  35 #define CONFIG_SYS_CLK_FREQ             100000000
  36 #define CONFIG_DDR_CLK_FREQ             100000000
  37
  38 #define DDR_SDRAM_CFG                   0x470c0008
  39 #define DDR_CS0_BNDS                    0x008000bf
  40 #define DDR_CS0_CONFIG                  0x80014302
  41 #define DDR_TIMING_CFG_0                0x50550004
  42 #define DDR_TIMING_CFG_1                0xbcb38c56
  43 #define DDR_TIMING_CFG_2                0x0040d120
  44 #define DDR_TIMING_CFG_3                0x010e1000
  45 #define DDR_TIMING_CFG_4                0x00000001
  46 #define DDR_TIMING_CFG_5                0x03401400
  47 #define DDR_SDRAM_CFG_2                 0x00401010
  48 #define DDR_SDRAM_MODE                  0x00061c60
  49 #define DDR_SDRAM_MODE_2                0x00180000
  50 #define DDR_SDRAM_INTERVAL              0x18600618
  51 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  52 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  53 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  54 #define DDR_DDR_CDR1                    0x80040000
  55 #define DDR_DDR_CDR2                    0x00000001
  56 #define DDR_SDRAM_CLK_CNTL              0x02000000
  57 #define DDR_DDR_ZQ_CNTL                 0x89080600
  58 #define DDR_CS0_CONFIG_2                0
  59 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  60
  61 #ifdef CONFIG_RAMBOOT_PBL
  62 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  63 #endif
  64
  65 #ifdef CONFIG_SD_BOOT
  66 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
  67 #define CONFIG_SPL_FRAMEWORK
  68 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  69 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  70 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  71 #define CONFIG_SPL_ENV_SUPPORT
  72 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  73 #define CONFIG_SPL_I2C_SUPPORT
  74 #define CONFIG_SPL_WATCHDOG_SUPPORT
  75 #define CONFIG_SPL_SERIAL_SUPPORT
  76 #define CONFIG_SPL_MMC_SUPPORT
  77 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  78 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
  79
  80 #define CONFIG_SPL_TEXT_BASE            0x10000000
  81 #define CONFIG_SPL_MAX_SIZE             0x1a000
  82 #define CONFIG_SPL_STACK                0x1001d000
  83 #define CONFIG_SPL_PAD_TO               0x1c000
  84 #define CONFIG_SYS_TEXT_BASE            0x82000000
  85
  86 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  87 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  88 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  89 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  90 #define CONFIG_SYS_MONITOR_LEN          0x80000
  91 #endif
  92
  93 #ifdef CONFIG_QSPI_BOOT
  94 #define CONFIG_SYS_TEXT_BASE            0x40010000
  95 #define CONFIG_SYS_NO_FLASH
  96 #endif
  97
  98 #ifndef CONFIG_SYS_TEXT_BASE
  99 #define CONFIG_SYS_TEXT_BASE            0x60100000
 100 #endif
 101
 102 #define CONFIG_NR_DRAM_BANKS            1
 103 #define PHYS_SDRAM                      0x80000000
 104 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 105
 106 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 107 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 108
 109 #define CONFIG_SYS_HAS_SERDES
 110
 111 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 112
 113 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 114         !defined(CONFIG_QSPI_BOOT)
 115 #define CONFIG_U_QE
 116 #endif
 117
 118 /*
 119  * IFC Definitions
 120  */
 121 #ifndef CONFIG_QSPI_BOOT
 122 #define CONFIG_FSL_IFC
 123 #define CONFIG_SYS_FLASH_BASE           0x60000000
 124 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 125
 126 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 127 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 128                                 CSPR_PORT_SIZE_16 | \
 129                                 CSPR_MSEL_NOR | \
 130                                 CSPR_V)
 131 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 132
 133 /* NOR Flash Timing Params */
 134 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 135                                         CSOR_NOR_TRHZ_80)
 136 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 137                                         FTIM0_NOR_TEADC(0x5) | \
 138                                         FTIM0_NOR_TAVDS(0x0) | \
 139                                         FTIM0_NOR_TEAHC(0x5))
 140 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 141                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 142                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 143 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 144                                         FTIM2_NOR_TCH(0x4) | \
 145                                         FTIM2_NOR_TWP(0x1c) | \
 146                                         FTIM2_NOR_TWPH(0x0e))
 147 #define CONFIG_SYS_NOR_FTIM3            0
 148
 149 #define CONFIG_FLASH_CFI_DRIVER
 150 #define CONFIG_SYS_FLASH_CFI
 151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 152 #define CONFIG_SYS_FLASH_QUIET_TEST
 153 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 156 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 157 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 158 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 159
 160 #define CONFIG_SYS_FLASH_EMPTY_INFO
 161 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 162
 163 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 164 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 165 #endif
 166
 167 /* CPLD */
 168
 169 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 170 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 171
 172 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 173 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 174                                         CSPR_PORT_SIZE_8 | \
 175                                         CSPR_MSEL_GPCM | \
 176                                         CSPR_V)
 177 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 178 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 179                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 180                                         CSOR_NOR_TRHZ_80)
 181
 182 /* CPLD Timing parameters for IFC GPCM */
 183 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 184                                         FTIM0_GPCM_TEADC(0xf) | \
 185                                         FTIM0_GPCM_TEAHC(0xf))
 186 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 187                                         FTIM1_GPCM_TRAD(0x3f))
 188 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 189                                         FTIM2_GPCM_TCH(0xf) | \
 190                                         FTIM2_GPCM_TWP(0xff))
 191 #define CONFIG_SYS_FPGA_FTIM3           0x0
 192 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 193 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 194 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 195 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 196 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 197 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 198 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 199 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 200 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 201 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 202 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 203 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 204 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 205 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 206 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 207 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 208
 209 /*
 210  * Serial Port
 211  */
 212 #ifdef CONFIG_LPUART
 213 #define CONFIG_FSL_LPUART
 214 #define CONFIG_LPUART_32B_REG
 215 #else
 216 #define CONFIG_CONS_INDEX               1
 217 #define CONFIG_SYS_NS16550
 218 #define CONFIG_SYS_NS16550_SERIAL
 219 #define CONFIG_SYS_NS16550_REG_SIZE     1
 220 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 221 #endif
 222
 223 #define CONFIG_BAUDRATE                 115200
 224
 225 /*
 226  * I2C
 227  */
 228 #define CONFIG_CMD_I2C
 229 #define CONFIG_SYS_I2C
 230 #define CONFIG_SYS_I2C_MXC
 231 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 232
 233 /* EEPROM */
 234 #ifndef CONFIG_SD_BOOT
 235 #define CONFIG_ID_EEPROM
 236 #define CONFIG_SYS_I2C_EEPROM_NXID
 237 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 242 #endif
 243
 244 /*
 245  * MMC
 246  */
 247 #define CONFIG_MMC
 248 #define CONFIG_CMD_MMC
 249 #define CONFIG_FSL_ESDHC
 250 #define CONFIG_GENERIC_MMC
 251
 252 #define CONFIG_CMD_FAT
 253 #define CONFIG_DOS_PARTITION
 254
 255 /* SPI */
 256 #ifdef CONFIG_QSPI_BOOT
 257 /* QSPI */
 258 #define CONFIG_FSL_QSPI
 259 #define QSPI0_AMBA_BASE                 0x40000000
 260 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 261 #define FSL_QSPI_FLASH_NUM              2
 262 #define CONFIG_SPI_FLASH_STMICRO
 263
 264 /* DM SPI */
 265 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 266 #define CONFIG_CMD_SF
 267 #define CONFIG_DM_SPI_FLASH
 268 #endif
 269 #endif
 270
 271 /*
 272  * Video
 273  */
 274 #define CONFIG_FSL_DCU_FB
 275
 276 #ifdef CONFIG_FSL_DCU_FB
 277 #define CONFIG_VIDEO
 278 #define CONFIG_CMD_BMP
 279 #define CONFIG_CFB_CONSOLE
 280 #define CONFIG_VGA_AS_SINGLE_DEVICE
 281 #define CONFIG_VIDEO_LOGO
 282 #define CONFIG_VIDEO_BMP_LOGO
 283
 284 #define CONFIG_FSL_DCU_SII9022A
 285 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 286 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 287 #endif
 288
 289 /*
 290  * eTSEC
 291  */
 292 #define CONFIG_TSEC_ENET
 293
 294 #ifdef CONFIG_TSEC_ENET
 295 #define CONFIG_MII
 296 #define CONFIG_MII_DEFAULT_TSEC         1
 297 #define CONFIG_TSEC1                    1
 298 #define CONFIG_TSEC1_NAME               "eTSEC1"
 299 #define CONFIG_TSEC2                    1
 300 #define CONFIG_TSEC2_NAME               "eTSEC2"
 301 #define CONFIG_TSEC3                    1
 302 #define CONFIG_TSEC3_NAME               "eTSEC3"
 303
 304 #define TSEC1_PHY_ADDR                  2
 305 #define TSEC2_PHY_ADDR                  0
 306 #define TSEC3_PHY_ADDR                  1
 307
 308 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 309 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 310 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 311
 312 #define TSEC1_PHYIDX                    0
 313 #define TSEC2_PHYIDX                    0
 314 #define TSEC3_PHYIDX                    0
 315
 316 #define CONFIG_ETHPRIME                 "eTSEC1"
 317
 318 #define CONFIG_PHY_GIGE
 319 #define CONFIG_PHYLIB
 320 #define CONFIG_PHY_ATHEROS
 321
 322 #define CONFIG_HAS_ETH0
 323 #define CONFIG_HAS_ETH1
 324 #define CONFIG_HAS_ETH2
 325 #endif
 326
 327 /* PCIe */
 328 #define CONFIG_PCI              /* Enable PCI/PCIE */
 329 #define CONFIG_PCIE1            /* PCIE controler 1 */
 330 #define CONFIG_PCIE2            /* PCIE controler 2 */
 331 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 332 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 333
 334 #define CONFIG_SYS_PCI_64BIT
 335
 336 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 337 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 338 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 339 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 340
 341 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 342 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 343 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 344
 345 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 346 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 347 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 348
 349 #ifdef CONFIG_PCI
 350 #define CONFIG_PCI_PNP
 351 #define CONFIG_E1000
 352 #define CONFIG_PCI_SCAN_SHOW
 353 #define CONFIG_CMD_PCI
 354 #endif
 355
 356 #define CONFIG_CMD_PING
 357 #define CONFIG_CMD_DHCP
 358 #define CONFIG_CMD_MII
 359
 360 #define CONFIG_CMDLINE_TAG
 361 #define CONFIG_CMDLINE_EDITING
 362
 363 #define CONFIG_ARMV7_NONSEC
 364 #define CONFIG_ARMV7_VIRT
 365 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 366 #define CONFIG_LS102XA_NS_ACCESS
 367 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 368 #define CONFIG_TIMER_CLK_FREQ           12500000
 369 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
 370
 371 #define CONFIG_HWCONFIG
 372 #define HWCONFIG_BUFFER_SIZE            128
 373
 374 #define CONFIG_BOOTDELAY                3
 375
 376 #ifdef CONFIG_LPUART
 377 #define CONFIG_EXTRA_ENV_SETTINGS       \
 378         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 379         "initrd_high=0xcfffffff\0"      \
 380         "fdt_high=0xcfffffff\0"
 381 #else
 382 #define CONFIG_EXTRA_ENV_SETTINGS       \
 383         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 384         "initrd_high=0xcfffffff\0"      \
 385         "fdt_high=0xcfffffff\0"
 386 #endif
 387
 388 /*
 389  * Miscellaneous configurable options
 390  */
 391 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 392 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 393 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 394 #define CONFIG_AUTO_COMPLETE
 395 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 396 #define CONFIG_SYS_PBSIZE               \
 397                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 398 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 399 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 400
 401 #define CONFIG_CMD_GREPENV
 402 #define CONFIG_CMD_MEMINFO
 403 #define CONFIG_CMD_MEMTEST
 404 #define CONFIG_SYS_MEMTEST_START        0x80000000
 405 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 406
 407 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 408
 409 #define CONFIG_LS102XA_STREAM_ID
 410
 411 /*
 412  * Stack sizes
 413  * The stack sizes are set up in start.S using the settings below
 414  */
 415 #define CONFIG_STACKSIZE                (30 * 1024)
 416
 417 #define CONFIG_SYS_INIT_SP_OFFSET \
 418         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 419 #define CONFIG_SYS_INIT_SP_ADDR \
 420         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 421
 422 #ifdef CONFIG_SPL_BUILD
 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 424 #else
 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 426 #endif
 427
 428 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
 429
 430 /*
 431  * Environment
 432  */
 433 #define CONFIG_ENV_OVERWRITE
 434
 435 #if defined(CONFIG_SD_BOOT)
 436 #define CONFIG_ENV_OFFSET               0x100000
 437 #define CONFIG_ENV_IS_IN_MMC
 438 #define CONFIG_SYS_MMC_ENV_DEV          0
 439 #define CONFIG_ENV_SIZE                 0x20000
 440 #elif defined(CONFIG_QSPI_BOOT)
 441 #define CONFIG_ENV_IS_IN_SPI_FLASH
 442 #define CONFIG_ENV_SIZE                 0x2000
 443 #define CONFIG_ENV_OFFSET               0x100000
 444 #define CONFIG_ENV_SECT_SIZE            0x10000
 445 #else
 446 #define CONFIG_ENV_IS_IN_FLASH
 447 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 448 #define CONFIG_ENV_SIZE                 0x20000
 449 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 450 #endif
 451
 452 #define CONFIG_OF_LIBFDT
 453 #define CONFIG_OF_BOARD_SETUP
 454 #define CONFIG_CMD_BOOTZ
 455
 456 #define CONFIG_MISC_INIT_R
 457
 458 /* Hash command with SHA acceleration supported in hardware */
 459 #define CONFIG_CMD_HASH
 460 #define CONFIG_SHA_HW_ACCEL
 461
 462 #ifdef CONFIG_SECURE_BOOT
 463 #define CONFIG_CMD_BLOB
 464 #endif
 465
 466 #endif