2 * Copyright (C) 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
11 #ifdef CONFIG_SPL_BUILD
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
29 #define CONFIG_REMAKE_ELF
30 #define CONFIG_FSL_LAYERSCAPE
34 #include <asm/arch/stream_id_lsch2.h>
35 #include <asm/arch/config.h>
37 /* Link Definitions */
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
40 #define CONFIG_SUPPORT_RAW_INITRD
42 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_VERY_BIG_RAM
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
50 #define CPU_RELEASE_ADDR secondary_boot_func
52 /* Generic Timer Definitions */
53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
55 /* Size of malloc() pool */
56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
59 #define CONFIG_CONS_INDEX 1
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE 1
62 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
68 #define CONFIG_SPL_FRAMEWORK
69 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
71 #define CONFIG_SPL_TEXT_BASE 0x10000000
72 #define CONFIG_SPL_MAX_SIZE 0x17000
73 #define CONFIG_SPL_STACK 0x1001e000
74 #define CONFIG_SPL_PAD_TO 0x1d000
76 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
77 CONFIG_SPL_BSS_MAX_SIZE)
78 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
79 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
80 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
82 #ifdef CONFIG_SECURE_BOOT
83 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
85 * HDR would be appended at end of image and copied to DDR along
86 * with U-Boot image. Here u-boot max. size is 512K. So if binary
87 * size increases then increase this size in case of secure boot as
88 * it uses raw u-boot image instead of fit image.
90 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
92 #define CONFIG_SYS_MONITOR_LEN 0x100000
93 #endif /* ifdef CONFIG_SECURE_BOOT */
97 #ifdef CONFIG_NAND_BOOT
98 #define CONFIG_SPL_PBL_PAD
99 #define CONFIG_SPL_FRAMEWORK
100 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
101 #define CONFIG_SPL_TEXT_BASE 0x10000000
102 #define CONFIG_SPL_MAX_SIZE 0x1a000
103 #define CONFIG_SPL_STACK 0x1001d000
104 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
106 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
107 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
108 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
109 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
111 #ifdef CONFIG_SECURE_BOOT
112 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
113 #endif /* ifdef CONFIG_SECURE_BOOT */
115 #ifdef CONFIG_U_BOOT_HDR_SIZE
117 * HDR would be appended at end of image and copied to DDR along
118 * with U-Boot image. Here u-boot max. size is 512K. So if binary
119 * size increases then increase this size in case of secure boot as
120 * it uses raw u-boot image instead of fit image.
122 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
124 #define CONFIG_SYS_MONITOR_LEN 0x100000
125 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
132 #define CONFIG_FSL_IFC
134 * CONFIG_SYS_FLASH_BASE has the final address (core view)
135 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
136 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
137 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
139 #define CONFIG_SYS_FLASH_BASE 0x60000000
140 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
141 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
143 #ifdef CONFIG_MTD_NOR_FLASH
144 #define CONFIG_FLASH_CFI_DRIVER
145 #define CONFIG_SYS_FLASH_CFI
146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
147 #define CONFIG_SYS_FLASH_QUIET_TEST
148 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
154 #define CONFIG_SYS_I2C
155 #define CONFIG_SYS_I2C_MXC
156 #define CONFIG_SYS_I2C_MXC_I2C1
157 #define CONFIG_SYS_I2C_MXC_I2C2
158 #define CONFIG_SYS_I2C_MXC_I2C3
159 #define CONFIG_SYS_I2C_MXC_I2C4
163 #define CONFIG_PCIE1 /* PCIE controller 1 */
164 #define CONFIG_PCIE2 /* PCIE controller 2 */
165 #define CONFIG_PCIE3 /* PCIE controller 3 */
168 #define CONFIG_PCI_SCAN_SHOW
172 /* Command line configuration */
177 #define CONFIG_FSL_ESDHC
178 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
184 #define CONFIG_FSL_DSPI
185 #ifdef CONFIG_FSL_DSPI
186 #define CONFIG_DM_SPI_FLASH
187 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
188 #define CONFIG_SPI_FLASH_SST /* cs1 */
189 #define CONFIG_SPI_FLASH_EON /* cs2 */
190 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
191 #define CONFIG_SF_DEFAULT_BUS 1
192 #define CONFIG_SF_DEFAULT_CS 0
197 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
201 #define CONFIG_SYS_DPAA_FMAN
202 #ifdef CONFIG_SYS_DPAA_FMAN
203 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
205 #ifdef CONFIG_NAND_BOOT
206 /* Store Fman ucode at offeset 0x900000(72 blocks). */
207 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
208 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
209 #elif defined(CONFIG_SD_BOOT)
211 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
212 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
213 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
215 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
216 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
217 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
218 #elif defined(CONFIG_QSPI_BOOT)
219 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
220 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
221 #define CONFIG_ENV_SPI_BUS 0
222 #define CONFIG_ENV_SPI_CS 0
223 #define CONFIG_ENV_SPI_MAX_HZ 1000000
224 #define CONFIG_ENV_SPI_MODE 0x03
226 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
227 /* FMan fireware Pre-load address */
228 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
229 #define CONFIG_SYS_QE_FW_ADDR 0x60940000
231 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
232 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
236 /* Miscellaneous configurable options */
237 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
239 #define CONFIG_HWCONFIG
240 #define HWCONFIG_BUFFER_SIZE 128
243 #include <config_distro_defaults.h>
244 #ifndef CONFIG_SPL_BUILD
245 #define BOOT_TARGET_DEVICES(func) \
248 #include <config_distro_bootcmd.h>
251 /* Initial environment variables */
252 #define CONFIG_EXTRA_ENV_SETTINGS \
253 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
254 "fdt_high=0xffffffffffffffff\0" \
255 "initrd_high=0xffffffffffffffff\0" \
256 "fdt_addr=0x64f00000\0" \
257 "kernel_addr=0x61000000\0" \
258 "scriptaddr=0x80000000\0" \
259 "scripthdraddr=0x80080000\0" \
260 "fdtheader_addr_r=0x80100000\0" \
261 "kernelheader_addr_r=0x80200000\0" \
262 "kernel_addr_r=0x81000000\0" \
263 "fdt_addr_r=0x90000000\0" \
264 "load_addr=0xa0000000\0" \
265 "kernelheader_addr=0x60800000\0" \
266 "kernel_size=0x2800000\0" \
267 "kernelheader_size=0x40000\0" \
268 "kernel_addr_sd=0x8000\0" \
269 "kernel_size_sd=0x14000\0" \
270 "kernelhdr_addr_sd=0x4000\0" \
271 "kernelhdr_size_sd=0x10\0" \
272 "console=ttyS0,115200\0" \
274 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
276 "boot_scripts=ls1043ardb_boot.scr\0" \
277 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
278 "scan_dev_for_boot_part=" \
279 "part list ${devtype} ${devnum} devplist; " \
280 "env exists devplist || setenv devplist 1; " \
281 "for distro_bootpart in ${devplist}; do " \
282 "if fstype ${devtype} " \
283 "${devnum}:${distro_bootpart} " \
284 "bootfstype; then " \
285 "run scan_dev_for_boot; " \
288 "scan_dev_for_boot=" \
289 "echo Scanning ${devtype} " \
290 "${devnum}:${distro_bootpart}...; " \
291 "for prefix in ${boot_prefixes}; do " \
292 "run scan_dev_for_scripts; " \
295 "load ${devtype} ${devnum}:${distro_bootpart} " \
296 "${scriptaddr} ${prefix}${script}; " \
297 "env exists secureboot && load ${devtype} " \
298 "${devnum}:${distro_bootpart} " \
299 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
300 "&& esbc_validate ${scripthdraddr};" \
301 "source ${scriptaddr}\0" \
302 "qspi_bootcmd=echo Trying load from qspi..;" \
303 "sf probe && sf read $load_addr " \
304 "$kernel_addr $kernel_size; env exists secureboot " \
305 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
306 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
307 "bootm $load_addr#$board\0" \
308 "nor_bootcmd=echo Trying load from nor..;" \
309 "cp.b $kernel_addr $load_addr " \
310 "$kernel_size; env exists secureboot " \
311 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
312 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
313 "bootm $load_addr#$board\0" \
314 "sd_bootcmd=echo Trying load from SD ..;" \
315 "mmcinfo; mmc read $load_addr " \
316 "$kernel_addr_sd $kernel_size_sd && " \
317 "env exists secureboot && mmc read $kernelheader_addr_r " \
318 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
319 " && esbc_validate ${kernelheader_addr_r};" \
320 "bootm $load_addr#$board\0"
323 #undef CONFIG_BOOTCOMMAND
324 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
325 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
326 "env exists secureboot && esbc_halt;"
327 #elif defined(CONFIG_SD_BOOT)
328 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
329 "env exists secureboot && esbc_halt;"
331 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
332 "env exists secureboot && esbc_halt;"
336 /* Monitor Command Prompt */
337 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
338 #define CONFIG_SYS_LONGHELP
341 #ifndef CONFIG_CMDLINE_EDITING
342 #define CONFIG_CMDLINE_EDITING 1
346 #define CONFIG_AUTO_COMPLETE
347 #define CONFIG_SYS_MAXARGS 64 /* max command args */
349 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
351 #include <asm/arch/soc.h>
353 #endif /* __LS1043A_COMMON_H */