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1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS1043ARDB_H__
8 #define __LS1043ARDB_H__
9
10 #include "ls1043a_common.h"
11
12 #define CONFIG_DISPLAY_CPUINFO
13 #define CONFIG_DISPLAY_BOARDINFO
14
15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
16 #define CONFIG_SYS_TEXT_BASE            0x82000000
17 #else
18 #define CONFIG_SYS_TEXT_BASE            0x60100000
19 #endif
20
21 #define CONFIG_SYS_CLK_FREQ             100000000
22 #define CONFIG_DDR_CLK_FREQ             100000000
23
24 #define CONFIG_LAYERSCAPE_NS_ACCESS
25 #define CONFIG_MISC_INIT_R
26
27 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
28 /* Physical Memory Map */
29 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
30 #define CONFIG_NR_DRAM_BANKS            1
31
32 #define CONFIG_SYS_SPD_BUS_NUM          0
33
34 #define CONFIG_FSL_DDR_BIST
35 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
36 #define CONFIG_SYS_DDR_RAW_TIMING
37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
38 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
39
40 #ifdef CONFIG_RAMBOOT_PBL
41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
42 #endif
43
44 #ifdef CONFIG_NAND_BOOT
45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
46 #endif
47
48 #ifdef CONFIG_SD_BOOT
49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
50 #endif
51
52 /*
53  * NOR Flash Definitions
54  */
55 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
56 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
57 #define CONFIG_SYS_NOR_CSPR                                     \
58         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
59         CSPR_PORT_SIZE_16                                       | \
60         CSPR_MSEL_NOR                                           | \
61         CSPR_V)
62
63 /* NOR Flash Timing Params */
64 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
65                                         CSOR_NOR_TRHZ_80)
66 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
67                                         FTIM0_NOR_TEADC(0x1) | \
68                                         FTIM0_NOR_TAVDS(0x0) | \
69                                         FTIM0_NOR_TEAHC(0xc))
70 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
71                                         FTIM1_NOR_TRAD_NOR(0xb) | \
72                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
73 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
74                                         FTIM2_NOR_TCH(0x4) | \
75                                         FTIM2_NOR_TWPH(0x8) | \
76                                         FTIM2_NOR_TWP(0x10))
77 #define CONFIG_SYS_NOR_FTIM3            0
78 #define CONFIG_SYS_IFC_CCR              0x01000000
79
80 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
81 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
82 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
83 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
84
85 #define CONFIG_SYS_FLASH_EMPTY_INFO
86 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
87
88 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
89 #define CONFIG_SYS_WRITE_SWAPPED_DATA
90
91 /*
92  * NAND Flash Definitions
93  */
94 #define CONFIG_NAND_FSL_IFC
95
96 #define CONFIG_SYS_NAND_BASE            0x7e800000
97 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
98
99 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
100 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
101                                 | CSPR_PORT_SIZE_8      \
102                                 | CSPR_MSEL_NAND        \
103                                 | CSPR_V)
104 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
105 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
106                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
107                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
108                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
109                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
110                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
111                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
112
113 #define CONFIG_SYS_NAND_ONFI_DETECTION
114
115 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
116                                         FTIM0_NAND_TWP(0x18)   | \
117                                         FTIM0_NAND_TWCHT(0x7) | \
118                                         FTIM0_NAND_TWH(0xa))
119 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
120                                         FTIM1_NAND_TWBE(0x39)  | \
121                                         FTIM1_NAND_TRR(0xe)   | \
122                                         FTIM1_NAND_TRP(0x18))
123 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
124                                         FTIM2_NAND_TREH(0xa) | \
125                                         FTIM2_NAND_TWHRE(0x1e))
126 #define CONFIG_SYS_NAND_FTIM3           0x0
127
128 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
129 #define CONFIG_SYS_MAX_NAND_DEVICE      1
130 #define CONFIG_MTD_NAND_VERIFY_WRITE
131 #define CONFIG_CMD_NAND
132
133 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
134
135 #ifdef CONFIG_NAND_BOOT
136 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
137 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
138 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
139 #endif
140
141 /*
142  * CPLD
143  */
144 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
145 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
146
147 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
148 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
149                                         CSPR_PORT_SIZE_8 | \
150                                         CSPR_MSEL_GPCM | \
151                                         CSPR_V)
152 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
153 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
154                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
155                                         CSOR_NOR_TRHZ_80)
156
157 /* CPLD Timing parameters for IFC GPCM */
158 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
159                                         FTIM0_GPCM_TEADC(0xf) | \
160                                         FTIM0_GPCM_TEAHC(0xf))
161 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
162                                         FTIM1_GPCM_TRAD(0x3f))
163 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
164                                         FTIM2_GPCM_TCH(0xf) | \
165                                         FTIM2_GPCM_TWP(0xff))
166 #define CONFIG_SYS_CPLD_FTIM3           0x0
167
168 /* IFC Timing Params */
169 #ifdef CONFIG_NAND_BOOT
170 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
171 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
172 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
173 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
174 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
175 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
176 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
177 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
178
179 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
180 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
181 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
182 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
183 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
184 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
185 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
186 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
187 #else
188 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
189 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
190 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
196
197 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
198 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
199 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
200 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
201 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
202 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
203 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
204 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
205 #endif
206
207 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
208 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
209 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
210 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
211 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
212 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
213 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
214 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
215
216 /* EEPROM */
217 #define CONFIG_ID_EEPROM
218 #define CONFIG_SYS_I2C_EEPROM_NXID
219 #define CONFIG_SYS_EEPROM_BUS_NUM               0
220 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
221 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
224
225 /*
226  * Environment
227  */
228 #define CONFIG_ENV_OVERWRITE
229
230 #if defined(CONFIG_NAND_BOOT)
231 #define CONFIG_ENV_IS_IN_NAND
232 #define CONFIG_ENV_SIZE                 0x2000
233 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
234 #elif defined(CONFIG_SD_BOOT)
235 #define CONFIG_ENV_OFFSET               (1024 * 1024)
236 #define CONFIG_ENV_IS_IN_MMC
237 #define CONFIG_SYS_MMC_ENV_DEV          0
238 #define CONFIG_ENV_SIZE                 0x2000
239 #else
240 #define CONFIG_ENV_IS_IN_FLASH
241 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
242 #define CONFIG_ENV_SECT_SIZE            0x20000
243 #define CONFIG_ENV_SIZE                 0x20000
244 #endif
245
246 /* FMan */
247 #ifdef CONFIG_SYS_DPAA_FMAN
248 #define CONFIG_FMAN_ENET
249 #define CONFIG_CMD_MII
250 #define CONFIG_PHYLIB
251 #define CONFIG_PHYLIB_10G
252 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
253
254 #define CONFIG_PHY_VITESSE
255 #define CONFIG_PHY_REALTEK
256 #define CONFIG_PHY_AQUANTIA
257
258 #define RGMII_PHY1_ADDR                 0x1
259 #define RGMII_PHY2_ADDR                 0x2
260
261 #define QSGMII_PORT1_PHY_ADDR           0x4
262 #define QSGMII_PORT2_PHY_ADDR           0x5
263 #define QSGMII_PORT3_PHY_ADDR           0x6
264 #define QSGMII_PORT4_PHY_ADDR           0x7
265
266 #define FM1_10GEC1_PHY_ADDR             0x1
267
268 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
269 #endif
270
271 #endif /* __LS1043ARDB_H__ */