git.sur5r.net Git - u-boot/blob - include/configs/ls1043ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043ARDB_H__
   8 #define __LS1043ARDB_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  13 #define CONFIG_SYS_TEXT_BASE            0x82000000
  14 #else
  15 #define CONFIG_SYS_TEXT_BASE            0x60100000
  16 #endif
  17
  18 #define CONFIG_SYS_CLK_FREQ             100000000
  19 #define CONFIG_DDR_CLK_FREQ             100000000
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22 #define CONFIG_MISC_INIT_R
  23
  24 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  25 /* Physical Memory Map */
  26 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  27 #define CONFIG_NR_DRAM_BANKS            2
  28
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #ifndef CONFIG_SPL
  32 #define CONFIG_SYS_DDR_RAW_TIMING
  33 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  34 #define CONFIG_FSL_DDR_BIST
  35 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  36 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  37 #endif
  38
  39 #ifdef CONFIG_RAMBOOT_PBL
  40 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  41 #endif
  42
  43 #ifdef CONFIG_NAND_BOOT
  44 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  45 #endif
  46
  47 #ifdef CONFIG_SD_BOOT
  48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  49 #define CONFIG_CMD_SPL
  50 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  51 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  52 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  53 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  54 #endif
  55
  56 /*
  57  * NOR Flash Definitions
  58  */
  59 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  60 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  61 #define CONFIG_SYS_NOR_CSPR                                     \
  62         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  63         CSPR_PORT_SIZE_16                                       | \
  64         CSPR_MSEL_NOR                                           | \
  65         CSPR_V)
  66
  67 /* NOR Flash Timing Params */
  68 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  69                                         CSOR_NOR_TRHZ_80)
  70 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  71                                         FTIM0_NOR_TEADC(0x1) | \
  72                                         FTIM0_NOR_TAVDS(0x0) | \
  73                                         FTIM0_NOR_TEAHC(0xc))
  74 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  75                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  76                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  77 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  78                                         FTIM2_NOR_TCH(0x4) | \
  79                                         FTIM2_NOR_TWPH(0x8) | \
  80                                         FTIM2_NOR_TWP(0x10))
  81 #define CONFIG_SYS_NOR_FTIM3            0
  82 #define CONFIG_SYS_IFC_CCR              0x01000000
  83
  84 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  85 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  86 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  87 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  88
  89 #define CONFIG_SYS_FLASH_EMPTY_INFO
  90 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  91
  92 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  93 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  94
  95 /*
  96  * NAND Flash Definitions
  97  */
  98 #ifndef SPL_NO_IFC
  99 #define CONFIG_NAND_FSL_IFC
 100 #endif
 101
 102 #define CONFIG_SYS_NAND_BASE            0x7e800000
 103 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 104
 105 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 106 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 107                                 | CSPR_PORT_SIZE_8      \
 108                                 | CSPR_MSEL_NAND        \
 109                                 | CSPR_V)
 110 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 111 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 112                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 113                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 114                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 115                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 116                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 117                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 118
 119 #define CONFIG_SYS_NAND_ONFI_DETECTION
 120
 121 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 122                                         FTIM0_NAND_TWP(0x18)   | \
 123                                         FTIM0_NAND_TWCHT(0x7) | \
 124                                         FTIM0_NAND_TWH(0xa))
 125 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 126                                         FTIM1_NAND_TWBE(0x39)  | \
 127                                         FTIM1_NAND_TRR(0xe)   | \
 128                                         FTIM1_NAND_TRP(0x18))
 129 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 130                                         FTIM2_NAND_TREH(0xa) | \
 131                                         FTIM2_NAND_TWHRE(0x1e))
 132 #define CONFIG_SYS_NAND_FTIM3           0x0
 133
 134 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 135 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 136 #define CONFIG_MTD_NAND_VERIFY_WRITE
 137
 138 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 139
 140 #ifdef CONFIG_NAND_BOOT
 141 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 142 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 143 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 144 #endif
 145
 146 /*
 147  * CPLD
 148  */
 149 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 150 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 151
 152 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 153 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 154                                         CSPR_PORT_SIZE_8 | \
 155                                         CSPR_MSEL_GPCM | \
 156                                         CSPR_V)
 157 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 158 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 159                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 160                                         CSOR_NOR_TRHZ_80)
 161
 162 /* CPLD Timing parameters for IFC GPCM */
 163 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 164                                         FTIM0_GPCM_TEADC(0xf) | \
 165                                         FTIM0_GPCM_TEAHC(0xf))
 166 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 167                                         FTIM1_GPCM_TRAD(0x3f))
 168 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 169                                         FTIM2_GPCM_TCH(0xf) | \
 170                                         FTIM2_GPCM_TWP(0xff))
 171 #define CONFIG_SYS_CPLD_FTIM3           0x0
 172
 173 /* IFC Timing Params */
 174 #ifdef CONFIG_NAND_BOOT
 175 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 176 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 177 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 178 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 179 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 180 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 181 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 182 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 183
 184 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 185 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 186 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 187 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 188 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 189 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 190 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 191 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 192 #else
 193 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 194 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 201
 202 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 203 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 204 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 205 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 206 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 207 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 208 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 209 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 210 #endif
 211
 212 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 213 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 214 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 215 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 216 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 217 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 218 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 219 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 220
 221 /* EEPROM */
 222 #ifndef SPL_NO_EEPROM
 223 #define CONFIG_ID_EEPROM
 224 #define CONFIG_SYS_I2C_EEPROM_NXID
 225 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 226 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 230 #endif
 231
 232 /*
 233  * Environment
 234  */
 235 #ifndef SPL_NO_ENV
 236 #define CONFIG_ENV_OVERWRITE
 237 #endif
 238
 239 #if defined(CONFIG_NAND_BOOT)
 240 #define CONFIG_ENV_SIZE                 0x2000
 241 #define CONFIG_ENV_OFFSET               (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 242 #elif defined(CONFIG_SD_BOOT)
 243 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 244 #define CONFIG_SYS_MMC_ENV_DEV          0
 245 #define CONFIG_ENV_SIZE                 0x2000
 246 #else
 247 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 248 #define CONFIG_ENV_SECT_SIZE            0x20000
 249 #define CONFIG_ENV_SIZE                 0x20000
 250 #endif
 251
 252 /* FMan */
 253 #ifndef SPL_NO_FMAN
 254 #define AQR105_IRQ_MASK                 0x40000000
 255
 256 #ifdef CONFIG_NET
 257 #define CONFIG_PHY_VITESSE
 258 #define CONFIG_PHY_REALTEK
 259 #endif
 260
 261 #ifdef CONFIG_SYS_DPAA_FMAN
 262 #define CONFIG_FMAN_ENET
 263 #define CONFIG_PHYLIB_10G
 264 #define CONFIG_PHY_AQUANTIA
 265
 266 #define RGMII_PHY1_ADDR                 0x1
 267 #define RGMII_PHY2_ADDR                 0x2
 268
 269 #define QSGMII_PORT1_PHY_ADDR           0x4
 270 #define QSGMII_PORT2_PHY_ADDR           0x5
 271 #define QSGMII_PORT3_PHY_ADDR           0x6
 272 #define QSGMII_PORT4_PHY_ADDR           0x7
 273
 274 #define FM1_10GEC1_PHY_ADDR             0x1
 275
 276 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 277 #endif
 278 #endif
 279
 280 /* QE */
 281 #ifndef SPL_NO_QE
 282 #if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
 283 #define CONFIG_U_QE
 284 #endif
 285 #endif
 286
 287 /* SATA */
 288 #ifndef SPL_NO_SATA
 289 #define CONFIG_LIBATA
 290 #define CONFIG_SCSI_AHCI
 291 #ifndef CONFIG_CMD_EXT2
 292 #define CONFIG_CMD_EXT2
 293 #endif
 294 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 295 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 296 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 297                                                 CONFIG_SYS_SCSI_MAX_LUN)
 298 #define SCSI_VEND_ID 0x1b4b
 299 #define SCSI_DEV_ID  0x9170
 300 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 301 #endif
 302
 303 #include <asm/fsl_secure_boot.h>
 304
 305 #endif /* __LS1043ARDB_H__ */