git.sur5r.net Git - u-boot/blob - include/configs/ls1043ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043ARDB_H__
   8 #define __LS1043ARDB_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #define CONFIG_SYS_CLK_FREQ             100000000
  13 #define CONFIG_DDR_CLK_FREQ             100000000
  14
  15 #define CONFIG_LAYERSCAPE_NS_ACCESS
  16 #define CONFIG_MISC_INIT_R
  17
  18 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  19 /* Physical Memory Map */
  20 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  21 #define CONFIG_NR_DRAM_BANKS            2
  22
  23 #define CONFIG_SYS_SPD_BUS_NUM          0
  24
  25 #ifndef CONFIG_SPL
  26 #define CONFIG_SYS_DDR_RAW_TIMING
  27 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  28 #define CONFIG_FSL_DDR_BIST
  29 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  30 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  31 #endif
  32
  33 #ifdef CONFIG_RAMBOOT_PBL
  34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  35 #endif
  36
  37 #ifdef CONFIG_NAND_BOOT
  38 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  39 #endif
  40
  41 #ifdef CONFIG_SD_BOOT
  42 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  43 #define CONFIG_CMD_SPL
  44 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  45 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  46 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  47 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  48 #endif
  49
  50 /*
  51  * NOR Flash Definitions
  52  */
  53 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  54 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  55 #define CONFIG_SYS_NOR_CSPR                                     \
  56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  57         CSPR_PORT_SIZE_16                                       | \
  58         CSPR_MSEL_NOR                                           | \
  59         CSPR_V)
  60
  61 /* NOR Flash Timing Params */
  62 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  63                                         CSOR_NOR_TRHZ_80)
  64 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  65                                         FTIM0_NOR_TEADC(0x1) | \
  66                                         FTIM0_NOR_TAVDS(0x0) | \
  67                                         FTIM0_NOR_TEAHC(0xc))
  68 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  69                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  70                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  71 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  72                                         FTIM2_NOR_TCH(0x4) | \
  73                                         FTIM2_NOR_TWPH(0x8) | \
  74                                         FTIM2_NOR_TWP(0x10))
  75 #define CONFIG_SYS_NOR_FTIM3            0
  76 #define CONFIG_SYS_IFC_CCR              0x01000000
  77
  78 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  79 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  80 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  81 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  82
  83 #define CONFIG_SYS_FLASH_EMPTY_INFO
  84 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  85
  86 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  87 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  88
  89 /*
  90  * NAND Flash Definitions
  91  */
  92 #ifndef SPL_NO_IFC
  93 #define CONFIG_NAND_FSL_IFC
  94 #endif
  95
  96 #define CONFIG_SYS_NAND_BASE            0x7e800000
  97 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  98
  99 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 100 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 101                                 | CSPR_PORT_SIZE_8      \
 102                                 | CSPR_MSEL_NAND        \
 103                                 | CSPR_V)
 104 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 105 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 106                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 107                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 108                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 109                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 110                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 111                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 112
 113 #define CONFIG_SYS_NAND_ONFI_DETECTION
 114
 115 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 116                                         FTIM0_NAND_TWP(0x18)   | \
 117                                         FTIM0_NAND_TWCHT(0x7) | \
 118                                         FTIM0_NAND_TWH(0xa))
 119 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 120                                         FTIM1_NAND_TWBE(0x39)  | \
 121                                         FTIM1_NAND_TRR(0xe)   | \
 122                                         FTIM1_NAND_TRP(0x18))
 123 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 124                                         FTIM2_NAND_TREH(0xa) | \
 125                                         FTIM2_NAND_TWHRE(0x1e))
 126 #define CONFIG_SYS_NAND_FTIM3           0x0
 127
 128 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 129 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 130 #define CONFIG_MTD_NAND_VERIFY_WRITE
 131
 132 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 133
 134 #ifdef CONFIG_NAND_BOOT
 135 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 136 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 137 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 138 #endif
 139
 140 /*
 141  * CPLD
 142  */
 143 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 144 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 145
 146 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 147 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 148                                         CSPR_PORT_SIZE_8 | \
 149                                         CSPR_MSEL_GPCM | \
 150                                         CSPR_V)
 151 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 152 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 153                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 154                                         CSOR_NOR_TRHZ_80)
 155
 156 /* CPLD Timing parameters for IFC GPCM */
 157 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 158                                         FTIM0_GPCM_TEADC(0xf) | \
 159                                         FTIM0_GPCM_TEAHC(0xf))
 160 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 161                                         FTIM1_GPCM_TRAD(0x3f))
 162 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 163                                         FTIM2_GPCM_TCH(0xf) | \
 164                                         FTIM2_GPCM_TWP(0xff))
 165 #define CONFIG_SYS_CPLD_FTIM3           0x0
 166
 167 /* IFC Timing Params */
 168 #ifdef CONFIG_NAND_BOOT
 169 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 170 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 171 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 172 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 173 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 174 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 175 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 176 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 177
 178 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 179 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 180 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 181 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 182 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 183 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 184 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 185 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 186 #else
 187 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 188 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 189 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 190 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 191 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 192 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 193 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 194 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 195
 196 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 197 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 198 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 199 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 200 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 201 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 202 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 203 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 204 #endif
 205
 206 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 207 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 208 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 209 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 210 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 211 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 212 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 213 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 214
 215 /* EEPROM */
 216 #ifndef SPL_NO_EEPROM
 217 #define CONFIG_ID_EEPROM
 218 #define CONFIG_SYS_I2C_EEPROM_NXID
 219 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 220 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 221 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 224 #endif
 225
 226 /*
 227  * Environment
 228  */
 229 #ifndef SPL_NO_ENV
 230 #define CONFIG_ENV_OVERWRITE
 231 #endif
 232
 233 #if defined(CONFIG_NAND_BOOT)
 234 #define CONFIG_ENV_SIZE                 0x2000
 235 #define CONFIG_ENV_OFFSET               (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 236 #elif defined(CONFIG_SD_BOOT)
 237 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 238 #define CONFIG_SYS_MMC_ENV_DEV          0
 239 #define CONFIG_ENV_SIZE                 0x2000
 240 #else
 241 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 242 #define CONFIG_ENV_SECT_SIZE            0x20000
 243 #define CONFIG_ENV_SIZE                 0x20000
 244 #endif
 245
 246 /* FMan */
 247 #ifndef SPL_NO_FMAN
 248 #define AQR105_IRQ_MASK                 0x40000000
 249
 250 #ifdef CONFIG_NET
 251 #define CONFIG_PHY_VITESSE
 252 #define CONFIG_PHY_REALTEK
 253 #endif
 254
 255 #ifdef CONFIG_SYS_DPAA_FMAN
 256 #define CONFIG_FMAN_ENET
 257 #define CONFIG_PHYLIB_10G
 258 #define CONFIG_PHY_AQUANTIA
 259
 260 #define RGMII_PHY1_ADDR                 0x1
 261 #define RGMII_PHY2_ADDR                 0x2
 262
 263 #define QSGMII_PORT1_PHY_ADDR           0x4
 264 #define QSGMII_PORT2_PHY_ADDR           0x5
 265 #define QSGMII_PORT3_PHY_ADDR           0x6
 266 #define QSGMII_PORT4_PHY_ADDR           0x7
 267
 268 #define FM1_10GEC1_PHY_ADDR             0x1
 269
 270 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 271 #endif
 272 #endif
 273
 274 /* QE */
 275 #ifndef SPL_NO_QE
 276 #if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
 277 #define CONFIG_U_QE
 278 #endif
 279 #endif
 280
 281 /* SATA */
 282 #ifndef SPL_NO_SATA
 283 #ifndef CONFIG_CMD_EXT2
 284 #define CONFIG_CMD_EXT2
 285 #endif
 286 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 287 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 288 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 289                                                 CONFIG_SYS_SCSI_MAX_LUN)
 290 #define SCSI_VEND_ID 0x1b4b
 291 #define SCSI_DEV_ID  0x9170
 292 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 293 #endif
 294
 295 #include <asm/fsl_secure_boot.h>
 296
 297 #endif /* __LS1043ARDB_H__ */