git.sur5r.net Git - u-boot/blob - include/configs/ls1043ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043ARDB_H__
   8 #define __LS1043ARDB_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #define CONFIG_DISPLAY_CPUINFO
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #define CONFIG_SYS_TEXT_BASE            0x60100000
  16
  17 #define CONFIG_SYS_CLK_FREQ             100000000
  18 #define CONFIG_DDR_CLK_FREQ             100000000
  19
  20 #define CONFIG_LAYERSCAPE_NS_ACCESS
  21 #define CONFIG_MISC_INIT_R
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26 #define CONFIG_NR_DRAM_BANKS            1
  27
  28 #define CONFIG_SYS_SPD_BUS_NUM          0
  29
  30 #define CONFIG_FSL_DDR_BIST
  31 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  32 #define CONFIG_SYS_DDR_RAW_TIMING
  33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  34 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  35
  36 /*
  37  * NOR Flash Definitions
  38  */
  39 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  40 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  41 #define CONFIG_SYS_NOR_CSPR                                     \
  42         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  43         CSPR_PORT_SIZE_16                                       | \
  44         CSPR_MSEL_NOR                                           | \
  45         CSPR_V)
  46
  47 /* NOR Flash Timing Params */
  48 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  49                                         CSOR_NOR_TRHZ_80)
  50 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  51                                         FTIM0_NOR_TEADC(0x1) | \
  52                                         FTIM0_NOR_TAVDS(0x0) | \
  53                                         FTIM0_NOR_TEAHC(0xc))
  54 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  55                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  56                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  57 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  58                                         FTIM2_NOR_TCH(0x4) | \
  59                                         FTIM2_NOR_TWPH(0x8) | \
  60                                         FTIM2_NOR_TWP(0x10))
  61 #define CONFIG_SYS_NOR_FTIM3            0
  62 #define CONFIG_SYS_IFC_CCR              0x01000000
  63
  64 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  65 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  66 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  67 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  68
  69 #define CONFIG_SYS_FLASH_EMPTY_INFO
  70 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  71
  72 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  73 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  74
  75 /*
  76  * NAND Flash Definitions
  77  */
  78 #define CONFIG_NAND_FSL_IFC
  79
  80 #define CONFIG_SYS_NAND_BASE            0x7e800000
  81 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  82
  83 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  84 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  85                                 | CSPR_PORT_SIZE_8      \
  86                                 | CSPR_MSEL_NAND        \
  87                                 | CSPR_V)
  88 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  89 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  90                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  91                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  92                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  93                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  94                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  95                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  96
  97 #define CONFIG_SYS_NAND_ONFI_DETECTION
  98
  99 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 100                                         FTIM0_NAND_TWP(0x18)   | \
 101                                         FTIM0_NAND_TWCHT(0x7) | \
 102                                         FTIM0_NAND_TWH(0xa))
 103 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 104                                         FTIM1_NAND_TWBE(0x39)  | \
 105                                         FTIM1_NAND_TRR(0xe)   | \
 106                                         FTIM1_NAND_TRP(0x18))
 107 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 108                                         FTIM2_NAND_TREH(0xa) | \
 109                                         FTIM2_NAND_TWHRE(0x1e))
 110 #define CONFIG_SYS_NAND_FTIM3           0x0
 111
 112 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 113 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 114 #define CONFIG_MTD_NAND_VERIFY_WRITE
 115 #define CONFIG_CMD_NAND
 116
 117 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 118
 119 /*
 120  * CPLD
 121  */
 122 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 123 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 124
 125 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 126 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 127                                         CSPR_PORT_SIZE_8 | \
 128                                         CSPR_MSEL_GPCM | \
 129                                         CSPR_V)
 130 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 131 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 132                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 133                                         CSOR_NOR_TRHZ_80)
 134
 135 /* CPLD Timing parameters for IFC GPCM */
 136 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 137                                         FTIM0_GPCM_TEADC(0xf) | \
 138                                         FTIM0_GPCM_TEAHC(0xf))
 139 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 140                                         FTIM1_GPCM_TRAD(0x3f))
 141 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 142                                         FTIM2_GPCM_TCH(0xf) | \
 143                                         FTIM2_GPCM_TWP(0xff))
 144 #define CONFIG_SYS_CPLD_FTIM3           0x0
 145
 146 /* IFC Timing Params */
 147 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 148 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 149 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 150 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 151 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 152 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 153 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 154 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 155
 156 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 157 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 158 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 159 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 160 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 161 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 162 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 163 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 164
 165 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 166 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 167 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 168 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 169 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 170 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 171 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 172 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 173
 174 /* EEPROM */
 175 #define CONFIG_ID_EEPROM
 176 #define CONFIG_SYS_I2C_EEPROM_NXID
 177 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 178 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 182
 183 /*
 184  * Environment
 185  */
 186 #define CONFIG_ENV_IS_IN_FLASH
 187 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 188 #define CONFIG_ENV_SECT_SIZE            0x20000
 189 #define CONFIG_ENV_SIZE                 0x20000
 190
 191 #endif /* __LS1043ARDB_H__ */