git.sur5r.net Git - u-boot/blob - include/configs/ls1088aqds.h

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1088A_QDS_H
   8 #define __LS1088A_QDS_H
   9
  10 #include "ls1088a_common.h"
  11
  12
  13 #define CONFIG_DISPLAY_BOARDINFO_LATE
  14
  15
  16 #ifndef __ASSEMBLY__
  17 unsigned long get_board_sys_clk(void);
  18 unsigned long get_board_ddr_clk(void);
  19 #endif
  20
  21
  22 #if defined(CONFIG_QSPI_BOOT)
  23 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  24 #define CONFIG_ENV_SECT_SIZE            0x40000
  25 #elif defined(CONFIG_SD_BOOT)
  26 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
  27 #define CONFIG_SYS_MMC_ENV_DEV          0
  28 #define CONFIG_ENV_SIZE                 0x2000
  29 #else
  30 #define CONFIG_ENV_IS_IN_FLASH
  31 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
  32 #define CONFIG_ENV_SECT_SIZE            0x20000
  33 #define CONFIG_ENV_SIZE                 0x20000
  34 #endif
  35
  36 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  37 #define CONFIG_QIXIS_I2C_ACCESS
  38 #define SYS_NO_FLASH
  39
  40 #undef CONFIG_CMD_IMLS
  41 #define CONFIG_SYS_CLK_FREQ             100000000
  42 #define CONFIG_DDR_CLK_FREQ             100000000
  43 #else
  44 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  45 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  46 #endif
  47
  48 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  49 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  50
  51 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  52
  53 #define CONFIG_DDR_SPD
  54 #define CONFIG_DDR_ECC
  55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  56 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  57 #define SPD_EEPROM_ADDRESS              0x51
  58 #define CONFIG_SYS_SPD_BUS_NUM          0
  59
  60
  61 /*
  62  * IFC Definitions
  63  */
  64 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  65 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  66 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  67 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  68
  69 #define CONFIG_SYS_NOR0_CSPR                                    \
  70         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  71         CSPR_PORT_SIZE_16                                       | \
  72         CSPR_MSEL_NOR                                           | \
  73         CSPR_V)
  74 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  75         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  76         CSPR_PORT_SIZE_16                                       | \
  77         CSPR_MSEL_NOR                                           | \
  78         CSPR_V)
  79 #define CONFIG_SYS_NOR1_CSPR                                    \
  80         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  81         CSPR_PORT_SIZE_16                                       | \
  82         CSPR_MSEL_NOR                                           | \
  83         CSPR_V)
  84 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  85         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  86         CSPR_PORT_SIZE_16                                       | \
  87         CSPR_MSEL_NOR                                           | \
  88         CSPR_V)
  89 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  90 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  91                                 FTIM0_NOR_TEADC(0x5) | \
  92                                 FTIM0_NOR_TEAHC(0x5))
  93 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  94                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  95                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  96 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  97                                 FTIM2_NOR_TCH(0x4) | \
  98                                 FTIM2_NOR_TWPH(0x0E) | \
  99                                 FTIM2_NOR_TWP(0x1c))
 100 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 101 #define CONFIG_SYS_IFC_CCR      0x01000000
 102
 103 #ifndef SYS_NO_FLASH
 104 #define CONFIG_FLASH_CFI_DRIVER
 105 #define CONFIG_SYS_FLASH_CFI
 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 107 #define CONFIG_SYS_FLASH_QUIET_TEST
 108 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 109
 110 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 111 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 112 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 113 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 114
 115 #define CONFIG_SYS_FLASH_EMPTY_INFO
 116 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 117                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 118 #endif
 119 #endif
 120
 121 #define CONFIG_NAND_FSL_IFC
 122 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 123 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 124
 125 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 126 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 127                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 128                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 129                                 | CSPR_V)
 130 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 131
 132 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 133                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 134                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 135                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 136                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 137                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 138                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 139
 140 #define CONFIG_SYS_NAND_ONFI_DETECTION
 141
 142 /* ONFI NAND Flash mode0 Timing Params */
 143 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 144                                         FTIM0_NAND_TWP(0x18)   | \
 145                                         FTIM0_NAND_TWCHT(0x07) | \
 146                                         FTIM0_NAND_TWH(0x0a))
 147 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 148                                         FTIM1_NAND_TWBE(0x39)  | \
 149                                         FTIM1_NAND_TRR(0x0e)   | \
 150                                         FTIM1_NAND_TRP(0x18))
 151 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 152                                         FTIM2_NAND_TREH(0x0a) | \
 153                                         FTIM2_NAND_TWHRE(0x1e))
 154 #define CONFIG_SYS_NAND_FTIM3           0x0
 155
 156 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 157 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 158 #define CONFIG_MTD_NAND_VERIFY_WRITE
 159 #define CONFIG_CMD_NAND
 160
 161 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 162
 163 #define CONFIG_FSL_QIXIS
 164 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 165 #define QIXIS_LBMAP_SWITCH              6
 166 #define QIXIS_QMAP_MASK                 0xe0
 167 #define QIXIS_QMAP_SHIFT                5
 168 #define QIXIS_LBMAP_MASK                0x0f
 169 #define QIXIS_LBMAP_SHIFT               0
 170 #define QIXIS_LBMAP_DFLTBANK            0x0e
 171 #define QIXIS_LBMAP_ALTBANK             0x2e
 172 #define QIXIS_LBMAP_SD                  0x00
 173 #define QIXIS_LBMAP_SD_QSPI             0x0e
 174 #define QIXIS_LBMAP_QSPI                0x0e
 175 #define QIXIS_RCW_SRC_SD                0x40
 176 #define QIXIS_RCW_SRC_QSPI              0x62
 177 #define QIXIS_RST_CTL_RESET             0x41
 178 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 179 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 180 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 181 #define QIXIS_RST_FORCE_MEM             0x01
 182 #define QIXIS_STAT_PRES1                0xb
 183 #define QIXIS_SDID_MASK                 0x07
 184 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 185
 186 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 187 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 188                                         | CSPR_PORT_SIZE_8 \
 189                                         | CSPR_MSEL_GPCM \
 190                                         | CSPR_V)
 191 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 192                                         | CSPR_PORT_SIZE_8 \
 193                                         | CSPR_MSEL_GPCM \
 194                                         | CSPR_V)
 195
 196 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 197 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 198 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 199 #else
 200 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 201 #endif
 202 /* QIXIS Timing parameters*/
 203 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 204                                         FTIM0_GPCM_TEADC(0x0e) | \
 205                                         FTIM0_GPCM_TEAHC(0x0e))
 206 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 207                                         FTIM1_GPCM_TRAD(0x3f))
 208 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 209                                         FTIM2_GPCM_TCH(0xf) | \
 210                                         FTIM2_GPCM_TWP(0x3E))
 211 #define SYS_FPGA_CS_FTIM3       0x0
 212
 213 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 216 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 217 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 218 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 219 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 220 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 221 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 222 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 223 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 224 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 225 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 226 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 227 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 228 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 229 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 230 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 231 #else
 232 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 233 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 234 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 235 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 236 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 237 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 238 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 239 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 240 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 241 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 242 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 243 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 244 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 245 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 246 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 247 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 248 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 249 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 250 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 251 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 252 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 253 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 254 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 255 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 256 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 257 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 258 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 259 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 260 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 261 #define CONFIG_SYS_CSPR3_FINAL          CONFIG_SYS_FPGA_CSPR_FINAL
 262 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 263 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 264 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_CS_FTIM0
 265 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_CS_FTIM1
 266 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_CS_FTIM2
 267 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_CS_FTIM3
 268 #endif
 269
 270 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 271
 272 /*
 273  * I2C bus multiplexer
 274  */
 275 #define I2C_MUX_PCA_ADDR_PRI            0x77
 276 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 277 #define I2C_RETIMER_ADDR                0x18
 278 #define I2C_RETIMER_ADDR2               0x19
 279 #define I2C_MUX_CH_DEFAULT              0x8
 280 #define I2C_MUX_CH5                     0xD
 281
 282 /*
 283 * RTC configuration
 284 */
 285 #define RTC
 286 #define CONFIG_RTC_PCF8563 1
 287 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 288 #define CONFIG_CMD_DATE
 289
 290 /* EEPROM */
 291 #define CONFIG_ID_EEPROM
 292 #define CONFIG_SYS_I2C_EEPROM_NXID
 293 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 294 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 295 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 296 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 298
 299 /* QSPI device */
 300 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 301 #define CONFIG_FSL_QSPI
 302 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 303 #define FSL_QSPI_FLASH_NUM              2
 304
 305 #endif
 306
 307 #ifdef CONFIG_FSL_DSPI
 308 #define CONFIG_SPI_FLASH_STMICRO
 309 #define CONFIG_SPI_FLASH_SST
 310 #define CONFIG_SPI_FLASH_EON
 311 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 312 #define CONFIG_SF_DEFAULT_BUS           1
 313 #define CONFIG_SF_DEFAULT_CS            0
 314 #endif
 315 #endif
 316
 317 #define CONFIG_CMD_MEMINFO
 318 #define CONFIG_CMD_MEMTEST
 319 #define CONFIG_SYS_MEMTEST_START        0x80000000
 320 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 321
 322 #ifdef CONFIG_SPL_BUILD
 323 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 324 #else
 325 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 326 #endif
 327
 328 #define CONFIG_FSL_MEMAC
 329
 330 /*  MMC  */
 331 #define CONFIG_FSL_ESDHC
 332 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 333 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 334         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 335
 336 /* Initial environment variables */
 337 #ifdef CONFIG_SECURE_BOOT
 338 #undef CONFIG_EXTRA_ENV_SETTINGS
 339 #define CONFIG_EXTRA_ENV_SETTINGS               \
 340         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 341         "loadaddr=0x90100000\0"                 \
 342         "kernel_addr=0x100000\0"                \
 343         "ramdisk_addr=0x800000\0"               \
 344         "ramdisk_size=0x2000000\0"              \
 345         "fdt_high=0xa0000000\0"                 \
 346         "initrd_high=0xffffffffffffffff\0"      \
 347         "kernel_start=0x1000000\0"              \
 348         "kernel_load=0xa0000000\0"              \
 349         "kernel_size=0x2800000\0"               \
 350         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;"  \
 351         "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
 352         "sf read 0xa0e00000 0xe00000 0x100000;" \
 353         "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;"  \
 354         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 355         "mcmemsize=0x70000000 \0"
 356 #else /* if !(CONFIG_SECURE_BOOT) */
 357 #if defined(CONFIG_QSPI_BOOT)
 358 #undef CONFIG_EXTRA_ENV_SETTINGS
 359 #define CONFIG_EXTRA_ENV_SETTINGS               \
 360         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 361         "loadaddr=0x90100000\0"                 \
 362         "kernel_addr=0x100000\0"                \
 363         "ramdisk_addr=0x800000\0"               \
 364         "ramdisk_size=0x2000000\0"              \
 365         "fdt_high=0xa0000000\0"                 \
 366         "initrd_high=0xffffffffffffffff\0"      \
 367         "kernel_start=0x1000000\0"              \
 368         "kernel_load=0xa0000000\0"              \
 369         "kernel_size=0x2800000\0"               \
 370         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 371         "sf read 0x80100000 0xE00000 0x100000;" \
 372         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 373         "mcmemsize=0x70000000 \0"
 374 #elif defined(CONFIG_SD_BOOT)
 375 #undef CONFIG_EXTRA_ENV_SETTINGS
 376 #define CONFIG_EXTRA_ENV_SETTINGS               \
 377         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 378         "loadaddr=0x90100000\0"                 \
 379         "kernel_addr=0x800\0"                \
 380         "ramdisk_addr=0x800000\0"               \
 381         "ramdisk_size=0x2000000\0"              \
 382         "fdt_high=0xa0000000\0"                 \
 383         "initrd_high=0xffffffffffffffff\0"      \
 384         "kernel_start=0x8000\0"              \
 385         "kernel_load=0xa0000000\0"              \
 386         "kernel_size=0x14000\0"               \
 387         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
 388         "mmc read 0x80100000 0x7000 0x800;" \
 389         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 390         "mcmemsize=0x70000000 \0"
 391 #else   /* NOR BOOT */
 392 #undef CONFIG_EXTRA_ENV_SETTINGS
 393 #define CONFIG_EXTRA_ENV_SETTINGS               \
 394         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 395         "loadaddr=0x90100000\0"                 \
 396         "kernel_addr=0x100000\0"                \
 397         "ramdisk_addr=0x800000\0"               \
 398         "ramdisk_size=0x2000000\0"              \
 399         "fdt_high=0xa0000000\0"                 \
 400         "initrd_high=0xffffffffffffffff\0"      \
 401         "kernel_start=0x1000000\0"              \
 402         "kernel_load=0xa0000000\0"              \
 403         "kernel_size=0x2800000\0"               \
 404         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 405         "mcmemsize=0x70000000 \0"
 406 #endif
 407 #endif /* CONFIG_SECURE_BOOT */
 408
 409 #ifdef CONFIG_FSL_MC_ENET
 410 #define CONFIG_FSL_MEMAC
 411 #define CONFIG_PHYLIB
 412 #define CONFIG_PHYLIB_10G
 413 #define CONFIG_PHY_VITESSE
 414 #define CONFIG_PHY_REALTEK
 415 #define CONFIG_PHY_TERANETICS
 416 #define RGMII_PHY1_ADDR         0x1
 417 #define RGMII_PHY2_ADDR         0x2
 418 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 419 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 420 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 421 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 422
 423 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 424 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 425 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 426 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 427 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 428 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 429 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 430 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 431 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 432 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 433 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 434 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 435 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 436 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 437 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 438 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 439
 440 #define CONFIG_MII              /* MII PHY management */
 441 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 442 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 443
 444 #endif
 445
 446 #undef CONFIG_CMDLINE_EDITING
 447 #include <config_distro_defaults.h>
 448 #define BOOT_TARGET_DEVICES(func) \
 449         func(USB, usb, 0) \
 450         func(MMC, mmc, 0) \
 451         func(SCSI, scsi, 0) \
 452         func(DHCP, dhcp, na)
 453 #include <config_distro_bootcmd.h>
 454
 455 #include <asm/fsl_secure_boot.h>
 456
 457 #endif /* __LS1088A_QDS_H */