3 * Copyright (C) 2014 Freescale Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_REMAKE_ELF
12 #define CONFIG_FSL_LAYERSCAPE
15 #define CONFIG_FSL_TZPC_BP147
17 #include <asm/arch/stream_id_lsch3.h>
18 #include <asm/arch/config.h>
20 /* Link Definitions */
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
23 /* We need architecture specific misc initializations */
25 /* Link Definitions */
26 #ifndef CONFIG_QSPI_BOOT
28 #define CONFIG_SYS_TEXT_BASE 0x80400000
30 #define CONFIG_SYS_TEXT_BASE 0x30100000
33 #define CONFIG_SYS_TEXT_BASE 0x20100000
34 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
35 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
36 #define CONFIG_ENV_SECT_SIZE 0x40000
39 #define CONFIG_SUPPORT_RAW_INITRD
41 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #ifndef CONFIG_SYS_FSL_DDR4
47 #define CONFIG_SYS_DDR_RAW_TIMING
50 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
52 #define CONFIG_VERY_BIG_RAM
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
57 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
62 #define CPU_RELEASE_ADDR secondary_boot_func
64 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
65 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
66 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
68 * DDR controller use 0 as the base address for binding.
69 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
71 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
72 #define CONFIG_DP_DDR_CTRL 2
73 #define CONFIG_DP_DDR_NUM_CTRLS 1
76 /* Generic Timer Definitions */
78 * This is not an accurate number. It is used in start.S. The frequency
79 * will be udpated later when get_bus_freq(0) is available.
81 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
83 /* Size of malloc() pool */
84 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
87 #define CONFIG_SYS_I2C
88 #define CONFIG_SYS_I2C_MXC
89 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
90 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
91 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
92 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
95 #define CONFIG_CONS_INDEX 1
96 #define CONFIG_SYS_NS16550_SERIAL
97 #define CONFIG_SYS_NS16550_REG_SIZE 1
98 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
100 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
103 #define CONFIG_FSL_IFC
106 * During booting, IFC is mapped at the region of 0x30000000.
107 * But this region is limited to 256MB. To accommodate NOR, promjet
108 * and FPGA. This region is divided as below:
109 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
110 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
111 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
113 * To accommodate bigger NOR flash and other devices, we will map IFC
114 * chip selects to as below:
115 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
116 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
117 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
118 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
119 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
121 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
122 * CONFIG_SYS_FLASH_BASE has the final address (core view)
123 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
124 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
125 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
128 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
129 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
130 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
132 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
133 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
136 unsigned long long get_qixis_addr(void);
138 #define QIXIS_BASE get_qixis_addr()
139 #define QIXIS_BASE_PHYS 0x20000000
140 #define QIXIS_BASE_PHYS_EARLY 0xC000000
141 #define QIXIS_STAT_PRES1 0xb
142 #define QIXIS_SDID_MASK 0x07
143 #define QIXIS_ESDHC_NO_ADAPTER 0x7
145 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
146 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
149 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
150 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
151 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
152 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
153 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
155 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
156 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
158 /* Define phy_reset function to boot the MC based on mcinitcmd.
159 * This happens late enough to properly fixup u-boot env MAC addresses.
161 #define CONFIG_RESET_PHY_R
164 * Carve out a DDR region which will not be used by u-boot/Linux
166 * It will be used by MC and Debug Server. The MC region must be
167 * 512MB aligned, so the min size to hide is 512MB.
169 #ifdef CONFIG_FSL_MC_ENET
170 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
173 /* Command line configuration */
175 /* Miscellaneous configurable options */
176 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
178 /* Physical Memory Map */
179 /* fixme: these need to be checked against the board */
180 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
182 #define CONFIG_NR_DRAM_BANKS 3
184 #define CONFIG_HWCONFIG
185 #define HWCONFIG_BUFFER_SIZE 128
187 /* Allow to overwrite serial and ethaddr */
188 #define CONFIG_ENV_OVERWRITE
190 /* Initial environment variables */
191 #define CONFIG_EXTRA_ENV_SETTINGS \
192 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
193 "loadaddr=0x80100000\0" \
194 "kernel_addr=0x100000\0" \
195 "ramdisk_addr=0x800000\0" \
196 "ramdisk_size=0x2000000\0" \
197 "fdt_high=0xa0000000\0" \
198 "initrd_high=0xffffffffffffffff\0" \
199 "kernel_start=0x581000000\0" \
200 "kernel_load=0xa0000000\0" \
201 "kernel_size=0x2800000\0" \
202 "console=ttyAMA0,38400n8\0" \
203 "mcinitcmd=fsl_mc start mc 0x580a00000" \
206 #ifdef CONFIG_SD_BOOT
207 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
208 " fsl_mc apply dpl 0x80200000 &&" \
209 " mmc read $kernel_load $kernel_start" \
210 " $kernel_size && bootm $kernel_load"
212 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
213 " cp.b $kernel_start $kernel_load" \
214 " $kernel_size && bootm $kernel_load"
217 /* Monitor Command Prompt */
218 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
219 #define CONFIG_SYS_LONGHELP
220 #define CONFIG_CMDLINE_EDITING 1
221 #define CONFIG_AUTO_COMPLETE
222 #define CONFIG_SYS_MAXARGS 64 /* max command args */
224 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
225 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
226 #define CONFIG_SPL_FRAMEWORK
227 #define CONFIG_SPL_MAX_SIZE 0x16000
228 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
229 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
230 #define CONFIG_SPL_TEXT_BASE 0x1800a000
232 #ifdef CONFIG_NAND_BOOT
233 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
234 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
236 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
237 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
238 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
240 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
242 #include <asm/arch/soc.h>
244 #endif /* __LS2_COMMON_H */