2 * Copyright 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #include "ls2080a_common.h"
12 #define CONFIG_SYS_CLK_FREQ 100000000
13 #define CONFIG_DDR_CLK_FREQ 133333333
15 #define CONFIG_DDR_SPD
16 #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
17 #define SPD_EEPROM_ADDRESS1 0x51
18 #define SPD_EEPROM_ADDRESS2 0x52
19 #define SPD_EEPROM_ADDRESS3 0x53
20 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
21 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
22 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
23 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
24 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
25 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
28 #define CONFIG_FSL_DDR_SYNC_REFRESH
30 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
31 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
33 * NOR Flash Timing Params
35 #define CONFIG_SYS_NOR0_CSPR \
36 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
40 #define CONFIG_SYS_NOR0_CSPR_EARLY \
41 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
45 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
46 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
47 FTIM0_NOR_TEADC(0x1) | \
49 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
50 FTIM1_NOR_TRAD_NOR(0x1))
51 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
52 FTIM2_NOR_TCH(0x0) | \
54 #define CONFIG_SYS_NOR_FTIM3 0x04000000
55 #define CONFIG_SYS_IFC_CCR 0x01000000
57 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
58 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
59 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
60 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
61 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
62 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
63 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
64 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
65 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
67 /* Debug Server firmware */
68 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
69 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
72 * This trick allows users to load MC images into DDR directly without
73 * copying from NOR flash. It dramatically improves speed.
75 #define CONFIG_SYS_LS_MC_FW_IN_DDR
76 #define CONFIG_SYS_LS_MC_DPL_IN_DDR
77 #define CONFIG_SYS_LS_MC_DPC_IN_DDR
79 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
81 /* Store environment at top of flash */
82 #define CONFIG_ENV_SIZE 0x1000
84 #endif /* __LS2_EMU_H */