]> git.sur5r.net Git - u-boot/blob - include/configs/ls2080ardb.h
spi: zynqmp_gqspi: Add support for ZynqMP qspi driver
[u-boot] / include / configs / ls2080ardb.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 NXP
4  * Copyright 2015 Freescale Semiconductor
5  */
6
7 #ifndef __LS2_RDB_H
8 #define __LS2_RDB_H
9
10 #include "ls2080a_common.h"
11
12 #ifdef CONFIG_FSL_QSPI
13 #ifdef CONFIG_TARGET_LS2081ARDB
14 #define CONFIG_QIXIS_I2C_ACCESS
15 #endif
16 #define CONFIG_SYS_I2C_EARLY_INIT
17 #endif
18
19 #define I2C_MUX_CH_VOL_MONITOR          0xa
20 #define I2C_VOL_MONITOR_ADDR            0x38
21 #define CONFIG_VOL_MONITOR_IR36021_READ
22 #define CONFIG_VOL_MONITOR_IR36021_SET
23
24 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
25 #ifndef CONFIG_SPL_BUILD
26 #define CONFIG_VID
27 #endif
28 /* step the IR regulator in 5mV increments */
29 #define IR_VDD_STEP_DOWN                5
30 #define IR_VDD_STEP_UP                  5
31 /* The lowest and highest voltage allowed for LS2080ARDB */
32 #define VDD_MV_MIN                      819
33 #define VDD_MV_MAX                      1212
34
35 #ifndef __ASSEMBLY__
36 unsigned long get_board_sys_clk(void);
37 #endif
38
39 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
40 #define CONFIG_DDR_CLK_FREQ             133333333
41 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
42
43 #define CONFIG_DDR_SPD
44 #define CONFIG_DDR_ECC
45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
46 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1     0x51
48 #define SPD_EEPROM_ADDRESS2     0x52
49 #define SPD_EEPROM_ADDRESS3     0x53
50 #define SPD_EEPROM_ADDRESS4     0x54
51 #define SPD_EEPROM_ADDRESS5     0x55
52 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
53 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
54 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
55 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
56 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
57 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
58 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
59 #endif
60 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
61
62 /* SATA */
63 #define CONFIG_SCSI_AHCI_PLAT
64
65 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
66 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
67
68 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
69 #define CONFIG_SYS_SCSI_MAX_LUN                 1
70 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
71                                                 CONFIG_SYS_SCSI_MAX_LUN)
72
73 #ifndef CONFIG_FSL_QSPI
74 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
75
76 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
77 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
78 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
79
80 #define CONFIG_SYS_NOR0_CSPR                                    \
81         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
82         CSPR_PORT_SIZE_16                                       | \
83         CSPR_MSEL_NOR                                           | \
84         CSPR_V)
85 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
86         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
87         CSPR_PORT_SIZE_16                                       | \
88         CSPR_MSEL_NOR                                           | \
89         CSPR_V)
90 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
91 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
92                                 FTIM0_NOR_TEADC(0x5) | \
93                                 FTIM0_NOR_TEAHC(0x5))
94 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
95                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
96                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
97 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
98                                 FTIM2_NOR_TCH(0x4) | \
99                                 FTIM2_NOR_TWPH(0x0E) | \
100                                 FTIM2_NOR_TWP(0x1c))
101 #define CONFIG_SYS_NOR_FTIM3    0x04000000
102 #define CONFIG_SYS_IFC_CCR      0x01000000
103
104 #ifdef CONFIG_MTD_NOR_FLASH
105 #define CONFIG_FLASH_CFI_DRIVER
106 #define CONFIG_SYS_FLASH_CFI
107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
108 #define CONFIG_SYS_FLASH_QUIET_TEST
109 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
110
111 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
112 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
113 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
114 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
115
116 #define CONFIG_SYS_FLASH_EMPTY_INFO
117 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
118                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
119 #endif
120
121 #define CONFIG_NAND_FSL_IFC
122 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
123 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
124
125 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
126 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
127                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
128                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
129                                 | CSPR_V)
130 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
131
132 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
133                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
134                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
135                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
136                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
137                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
138                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
139
140 #define CONFIG_SYS_NAND_ONFI_DETECTION
141
142 /* ONFI NAND Flash mode0 Timing Params */
143 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
144                                         FTIM0_NAND_TWP(0x30)   | \
145                                         FTIM0_NAND_TWCHT(0x0e) | \
146                                         FTIM0_NAND_TWH(0x14))
147 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
148                                         FTIM1_NAND_TWBE(0xab)  | \
149                                         FTIM1_NAND_TRR(0x1c)   | \
150                                         FTIM1_NAND_TRP(0x30))
151 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
152                                         FTIM2_NAND_TREH(0x14) | \
153                                         FTIM2_NAND_TWHRE(0x3c))
154 #define CONFIG_SYS_NAND_FTIM3           0x0
155
156 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
157 #define CONFIG_SYS_MAX_NAND_DEVICE      1
158 #define CONFIG_MTD_NAND_VERIFY_WRITE
159
160 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
161 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
162 #define QIXIS_LBMAP_SWITCH              0x06
163 #define QIXIS_LBMAP_MASK                0x0f
164 #define QIXIS_LBMAP_SHIFT               0
165 #define QIXIS_LBMAP_DFLTBANK            0x00
166 #define QIXIS_LBMAP_ALTBANK             0x04
167 #define QIXIS_LBMAP_NAND                0x09
168 #define QIXIS_RST_CTL_RESET             0x31
169 #define QIXIS_RST_CTL_RESET_EN          0x30
170 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
171 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
172 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
173 #define QIXIS_RCW_SRC_NAND              0x119
174 #define QIXIS_RST_FORCE_MEM             0x01
175
176 #define CONFIG_SYS_CSPR3_EXT    (0x0)
177 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
178                                 | CSPR_PORT_SIZE_8 \
179                                 | CSPR_MSEL_GPCM \
180                                 | CSPR_V)
181 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
182                                 | CSPR_PORT_SIZE_8 \
183                                 | CSPR_MSEL_GPCM \
184                                 | CSPR_V)
185
186 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
187 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
188 /* QIXIS Timing parameters for IFC CS3 */
189 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
190                                         FTIM0_GPCM_TEADC(0x0e) | \
191                                         FTIM0_GPCM_TEAHC(0x0e))
192 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
193                                         FTIM1_GPCM_TRAD(0x3f))
194 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
195                                         FTIM2_GPCM_TCH(0xf) | \
196                                         FTIM2_GPCM_TWP(0x3E))
197 #define CONFIG_SYS_CS3_FTIM3            0x0
198
199 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
200 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
201 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
202 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
203 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
204 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
205 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
206 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
207 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
208 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
209 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
210 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
211 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
212 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
213 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
214 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
215 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
216 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
217
218 #define CONFIG_ENV_OFFSET               (2048 * 1024)
219 #define CONFIG_ENV_SECT_SIZE            0x20000
220 #define CONFIG_ENV_SIZE                 0x2000
221 #define CONFIG_SPL_PAD_TO               0x80000
222 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
223 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
224 #else
225 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
226 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
227 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
228 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
229 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
230 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
231 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
232 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
233 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
234 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
235 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
236 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
237 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
238 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
239 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
240 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
241 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
242
243 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
244 #define CONFIG_ENV_SECT_SIZE            0x20000
245 #define CONFIG_ENV_SIZE                 0x2000
246 #endif
247
248 /* Debug Server firmware */
249 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
250 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
251 #endif
252 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
253
254 #ifdef CONFIG_TARGET_LS2081ARDB
255 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
256 #define QIXIS_QMAP_MASK                 0x07
257 #define QIXIS_QMAP_SHIFT                5
258 #define QIXIS_LBMAP_DFLTBANK            0x00
259 #define QIXIS_LBMAP_QSPI                0x00
260 #define QIXIS_RCW_SRC_QSPI              0x62
261 #define QIXIS_LBMAP_ALTBANK             0x20
262 #define QIXIS_RST_CTL_RESET             0x31
263 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
264 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
265 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
266 #define QIXIS_LBMAP_MASK                0x0f
267 #define QIXIS_RST_CTL_RESET_EN          0x30
268 #endif
269
270 /*
271  * I2C
272  */
273 #ifdef CONFIG_TARGET_LS2081ARDB
274 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
275 #endif
276 #define I2C_MUX_PCA_ADDR                0x75
277 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
278
279 /* I2C bus multiplexer */
280 #define I2C_MUX_CH_DEFAULT      0x8
281
282 /* SPI */
283 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
284 #define CONFIG_SPI_FLASH
285 #ifdef CONFIG_FSL_DSPI
286 #define CONFIG_SPI_FLASH_STMICRO
287 #endif
288 #ifdef CONFIG_FSL_QSPI
289 #define CONFIG_SPI_FLASH_SPANSION
290 #endif
291 #define FSL_QSPI_FLASH_SIZE             SZ_64M  /* 64MB */
292 #define FSL_QSPI_FLASH_NUM              2
293 #endif
294
295 /*
296  * RTC configuration
297  */
298 #define RTC
299 #ifdef CONFIG_TARGET_LS2081ARDB
300 #define CONFIG_RTC_PCF8563              1
301 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
302 #else
303 #define CONFIG_RTC_DS3231               1
304 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
305 #endif
306
307 /* EEPROM */
308 #define CONFIG_ID_EEPROM
309 #define CONFIG_SYS_I2C_EEPROM_NXID
310 #define CONFIG_SYS_EEPROM_BUS_NUM       0
311 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
312 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
315
316 #define CONFIG_FSL_MEMAC
317
318 #ifdef CONFIG_PCI
319 #define CONFIG_PCI_SCAN_SHOW
320 #endif
321
322 /*  MMC  */
323 #ifdef CONFIG_MMC
324 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
325 #endif
326
327 #define CONFIG_MISC_INIT_R
328
329 #define BOOT_TARGET_DEVICES(func) \
330         func(USB, usb, 0) \
331         func(MMC, mmc, 0) \
332         func(SCSI, scsi, 0) \
333         func(DHCP, dhcp, na)
334 #include <config_distro_bootcmd.h>
335
336 #ifdef CONFIG_QSPI_BOOT
337 #define MC_INIT_CMD                             \
338         "mcinitcmd=env exists secureboot && "   \
339         "esbc_validate 0x20700000 && "          \
340         "esbc_validate 0x20740000;"             \
341         "fsl_mc start mc 0x20a00000 0x20e00000 \0"
342 #elif defined(CONFIG_SD_BOOT)
343 #define MC_INIT_CMD                             \
344         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
345         "mmc read 0x80100000 0x7000 0x800;"     \
346         "env exists secureboot && "             \
347         "mmc read 0x80700000 0x3800 0x10 && "   \
348         "mmc read 0x80740000 0x3A00 0x10 && "   \
349         "esbc_validate 0x80700000 && "          \
350         "esbc_validate 0x80740000 ;"            \
351         "fsl_mc start mc 0x80000000 0x80100000\0" \
352         "mcmemsize=0x70000000\0"
353 #else
354 #define MC_INIT_CMD                             \
355         "mcinitcmd=env exists secureboot && "   \
356         "esbc_validate 0x580700000 && "         \
357         "esbc_validate 0x580740000; "           \
358         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
359 #endif
360
361 /* Initial environment variables */
362 #undef CONFIG_EXTRA_ENV_SETTINGS
363 #define CONFIG_EXTRA_ENV_SETTINGS               \
364         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
365         "ramdisk_addr=0x800000\0"               \
366         "ramdisk_size=0x2000000\0"              \
367         "fdt_high=0xa0000000\0"                 \
368         "initrd_high=0xffffffffffffffff\0"      \
369         "fdt_addr=0x64f00000\0"                 \
370         "kernel_addr=0x581000000\0"             \
371         "kernel_start=0x1000000\0"              \
372         "kernelheader_start=0x800000\0"         \
373         "scriptaddr=0x80000000\0"               \
374         "scripthdraddr=0x80080000\0"            \
375         "fdtheader_addr_r=0x80100000\0"         \
376         "kernelheader_addr_r=0x80200000\0"      \
377         "kernelheader_addr=0x580800000\0"       \
378         "kernel_addr_r=0x81000000\0"            \
379         "kernelheader_size=0x40000\0"           \
380         "fdt_addr_r=0x90000000\0"               \
381         "load_addr=0xa0000000\0"                \
382         "kernel_size=0x2800000\0"               \
383         "kernel_addr_sd=0x8000\0"               \
384         "kernel_size_sd=0x14000\0"              \
385         "console=ttyAMA0,38400n8\0"             \
386         "mcmemsize=0x70000000\0"                \
387         "sd_bootcmd=echo Trying load from SD ..;" \
388         "mmcinfo; mmc read $load_addr "         \
389         "$kernel_addr_sd $kernel_size_sd && "   \
390         "bootm $load_addr#$board\0"             \
391         MC_INIT_CMD                             \
392         BOOTENV                                 \
393         "boot_scripts=ls2088ardb_boot.scr\0"    \
394         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
395         "scan_dev_for_boot_part="               \
396                 "part list ${devtype} ${devnum} devplist; "     \
397                 "env exists devplist || setenv devplist 1; "    \
398                 "for distro_bootpart in ${devplist}; do "       \
399                         "if fstype ${devtype} "                 \
400                                 "${devnum}:${distro_bootpart} " \
401                                 "bootfstype; then "             \
402                                 "run scan_dev_for_boot; "       \
403                         "fi; "                                  \
404                 "done\0"                                        \
405         "scan_dev_for_boot="                                    \
406                 "echo Scanning ${devtype} "                     \
407                         "${devnum}:${distro_bootpart}...; "     \
408                 "for prefix in ${boot_prefixes}; do "           \
409                         "run scan_dev_for_scripts; "            \
410                 "done;\0"                                       \
411         "boot_a_script="                                        \
412                 "load ${devtype} ${devnum}:${distro_bootpart} " \
413                         "${scriptaddr} ${prefix}${script}; "    \
414                 "env exists secureboot && load ${devtype} "     \
415                         "${devnum}:${distro_bootpart} "         \
416                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
417                         "&& esbc_validate ${scripthdraddr};"    \
418                 "source ${scriptaddr}\0"                        \
419         "qspi_bootcmd=echo Trying load from qspi..;"            \
420                 "sf probe && sf read $load_addr "               \
421                 "$kernel_start $kernel_size ; env exists secureboot &&" \
422                 "sf read $kernelheader_addr_r $kernelheader_start "     \
423                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
424                 " bootm $load_addr#$board\0"                    \
425         "nor_bootcmd=echo Trying load from nor..;"              \
426                 "cp.b $kernel_addr $load_addr "                 \
427                 "$kernel_size ; env exists secureboot && "      \
428                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
429                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
430                 "bootm $load_addr#$board\0"
431
432 #undef CONFIG_BOOTCOMMAND
433 #ifdef CONFIG_QSPI_BOOT
434 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
435 #define CONFIG_BOOTCOMMAND                                              \
436                         "env exists mcinitcmd && env exists secureboot "\
437                         "&& esbc_validate 0x20780000; "                 \
438                         "env exists mcinitcmd && "                      \
439                         "fsl_mc lazyapply dpl 0x20d00000; "             \
440                         "run distro_bootcmd;run qspi_bootcmd; "         \
441                         "env exists secureboot && esbc_halt;"
442 #elif defined(CONFIG_SD_BOOT)
443 /* Try to boot an on-SD kernel first, then do normal distro boot */
444 #define CONFIG_BOOTCOMMAND                                              \
445                         "env exists mcinitcmd && env exists secureboot "\
446                         "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
447                         "&& esbc_validate $load_addr; "                 \
448                         "env exists mcinitcmd && run mcinitcmd "        \
449                         "&& mmc read 0x88000000 0x6800 0x800 "          \
450                         "&& fsl_mc lazyapply dpl 0x88000000; "          \
451                         "run distro_bootcmd;run sd_bootcmd; "           \
452                         "env exists secureboot && esbc_halt;"
453 #else
454 /* Try to boot an on-NOR kernel first, then do normal distro boot */
455 #define CONFIG_BOOTCOMMAND                                              \
456                         "env exists mcinitcmd && env exists secureboot "\
457                         "&& esbc_validate 0x580780000; env exists mcinitcmd "\
458                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
459                         "run distro_bootcmd;run nor_bootcmd; "          \
460                         "env exists secureboot && esbc_halt;"
461 #endif
462
463 /* MAC/PHY configuration */
464 #ifdef CONFIG_FSL_MC_ENET
465 #define CONFIG_PHYLIB_10G
466 #define CONFIG_PHY_AQUANTIA
467 #define CONFIG_PHY_CORTINA
468 #define CONFIG_SYS_CORTINA_FW_IN_NOR
469 #ifdef CONFIG_QSPI_BOOT
470 #define CONFIG_CORTINA_FW_ADDR          0x20980000
471 #else
472 #define CONFIG_CORTINA_FW_ADDR          0x580980000
473 #endif
474 #define CONFIG_CORTINA_FW_LENGTH        0x40000
475
476 #define CORTINA_PHY_ADDR1       0x10
477 #define CORTINA_PHY_ADDR2       0x11
478 #define CORTINA_PHY_ADDR3       0x12
479 #define CORTINA_PHY_ADDR4       0x13
480 #define AQ_PHY_ADDR1            0x00
481 #define AQ_PHY_ADDR2            0x01
482 #define AQ_PHY_ADDR3            0x02
483 #define AQ_PHY_ADDR4            0x03
484 #define AQR405_IRQ_MASK         0x36
485
486 #define CONFIG_MII
487 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
488 #define CONFIG_PHY_AQUANTIA
489 #endif
490
491 #include <asm/fsl_secure_boot.h>
492
493 #endif /* __LS2_RDB_H */