2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #include "ls2085a_common.h"
12 #define CONFIG_IDENT_STRING " LS2085A-QDS"
13 #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-QDS"
15 #define CONFIG_DISPLAY_BOARDINFO
18 unsigned long get_board_sys_clk(void);
19 unsigned long get_board_ddr_clk(void);
22 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
23 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
24 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
26 #define CONFIG_DDR_SPD
27 #define CONFIG_DDR_ECC
28 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
29 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
30 #define SPD_EEPROM_ADDRESS1 0x51
31 #define SPD_EEPROM_ADDRESS2 0x52
32 #define SPD_EEPROM_ADDRESS3 0x53
33 #define SPD_EEPROM_ADDRESS4 0x54
34 #define SPD_EEPROM_ADDRESS5 0x55
35 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
36 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
37 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
38 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
39 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
40 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
41 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
43 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
45 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
46 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
47 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
49 #define CONFIG_SYS_NOR0_CSPR \
50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
54 #define CONFIG_SYS_NOR0_CSPR_EARLY \
55 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
59 #define CONFIG_SYS_NOR1_CSPR \
60 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
64 #define CONFIG_SYS_NOR1_CSPR_EARLY \
65 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
69 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
70 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
71 FTIM0_NOR_TEADC(0x5) | \
73 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
74 FTIM1_NOR_TRAD_NOR(0x1a) |\
75 FTIM1_NOR_TSEQRAD_NOR(0x13))
76 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
77 FTIM2_NOR_TCH(0x4) | \
78 FTIM2_NOR_TWPH(0x0E) | \
80 #define CONFIG_SYS_NOR_FTIM3 0x04000000
81 #define CONFIG_SYS_IFC_CCR 0x01000000
83 #ifndef CONFIG_SYS_NO_FLASH
84 #define CONFIG_FLASH_CFI_DRIVER
85 #define CONFIG_SYS_FLASH_CFI
86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
87 #define CONFIG_SYS_FLASH_QUIET_TEST
88 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
90 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
91 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
92 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
93 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
95 #define CONFIG_SYS_FLASH_EMPTY_INFO
96 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
97 CONFIG_SYS_FLASH_BASE + 0x40000000}
100 #define CONFIG_NAND_FSL_IFC
101 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
102 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
105 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
106 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
107 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
108 | CSPR_MSEL_NAND /* MSEL = NAND */ \
110 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
112 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
113 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
114 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
115 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
116 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
117 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
118 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
120 #define CONFIG_SYS_NAND_ONFI_DETECTION
122 /* ONFI NAND Flash mode0 Timing Params */
123 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
124 FTIM0_NAND_TWP(0x18) | \
125 FTIM0_NAND_TWCHT(0x07) | \
126 FTIM0_NAND_TWH(0x0a))
127 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
128 FTIM1_NAND_TWBE(0x39) | \
129 FTIM1_NAND_TRR(0x0e) | \
130 FTIM1_NAND_TRP(0x18))
131 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
132 FTIM2_NAND_TREH(0x0a) | \
133 FTIM2_NAND_TWHRE(0x1e))
134 #define CONFIG_SYS_NAND_FTIM3 0x0
136 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
137 #define CONFIG_SYS_MAX_NAND_DEVICE 1
138 #define CONFIG_MTD_NAND_VERIFY_WRITE
139 #define CONFIG_CMD_NAND
141 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
143 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
144 #define QIXIS_LBMAP_SWITCH 0x06
145 #define QIXIS_LBMAP_MASK 0x0f
146 #define QIXIS_LBMAP_SHIFT 0
147 #define QIXIS_LBMAP_DFLTBANK 0x00
148 #define QIXIS_LBMAP_ALTBANK 0x04
149 #define QIXIS_LBMAP_NAND 0x09
150 #define QIXIS_RST_CTL_RESET 0x31
151 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
152 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
153 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
154 #define QIXIS_RCW_SRC_NAND 0x107
155 #define QIXIS_RST_FORCE_MEM 0x01
157 #define CONFIG_SYS_CSPR3_EXT (0x0)
158 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
162 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
167 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
168 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
169 /* QIXIS Timing parameters for IFC CS3 */
170 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
171 FTIM0_GPCM_TEADC(0x0e) | \
172 FTIM0_GPCM_TEAHC(0x0e))
173 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
174 FTIM1_GPCM_TRAD(0x3f))
175 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
176 FTIM2_GPCM_TCH(0xf) | \
177 FTIM2_GPCM_TWP(0x3E))
178 #define CONFIG_SYS_CS3_FTIM3 0x0
180 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
181 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
182 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
183 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
184 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
185 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
186 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
187 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
188 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
189 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
190 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
191 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
192 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
193 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
194 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
195 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
196 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
197 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
198 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
199 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
200 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
201 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
202 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
203 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
204 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
205 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
206 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
207 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
209 #define CONFIG_ENV_IS_IN_NAND
210 #define CONFIG_ENV_OFFSET (896 * 1024)
211 #define CONFIG_ENV_SECT_SIZE 0x20000
212 #define CONFIG_ENV_SIZE 0x2000
213 #define CONFIG_SPL_PAD_TO 0x20000
214 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
215 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
217 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
218 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
219 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
220 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
221 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
222 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
223 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
224 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
225 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
226 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
227 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
228 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
229 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
230 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
231 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
232 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
233 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
234 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
235 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
236 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
237 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
238 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
239 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
240 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
241 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
242 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
243 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
245 #define CONFIG_ENV_IS_IN_FLASH
246 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
247 #define CONFIG_ENV_SECT_SIZE 0x20000
248 #define CONFIG_ENV_SIZE 0x2000
251 /* Debug Server firmware */
252 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
253 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
256 #define CONFIG_SYS_LS_MC_FW_IN_NOR
257 #define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
259 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
260 #define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
262 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
263 #define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
265 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
270 #define I2C_MUX_PCA_ADDR 0x77
271 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
273 /* I2C bus multiplexer */
274 #define I2C_MUX_CH_DEFAULT 0x8
280 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
281 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
288 #define CONFIG_RTC_DS3231 1
289 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
292 #define CONFIG_ID_EEPROM
293 #define CONFIG_CMD_EEPROM
294 #define CONFIG_SYS_I2C_EEPROM_NXID
295 #define CONFIG_SYS_EEPROM_BUS_NUM 0
296 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
297 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
298 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
301 #define CONFIG_FSL_MEMAC
302 #define CONFIG_PCI /* Enable PCIE */
303 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
306 #define CONFIG_PCI_PNP
308 #define CONFIG_PCI_SCAN_SHOW
309 #define CONFIG_CMD_PCI
315 #define CONFIG_CMD_MMC
316 #define CONFIG_FSL_ESDHC
317 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
318 #define CONFIG_GENERIC_MMC
319 #define CONFIG_CMD_FAT
320 #define CONFIG_DOS_PARTITION
323 /* Initial environment variables */
324 #undef CONFIG_EXTRA_ENV_SETTINGS
325 #define CONFIG_EXTRA_ENV_SETTINGS \
326 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
327 "loadaddr=0x80100000\0" \
328 "kernel_addr=0x100000\0" \
329 "ramdisk_addr=0x800000\0" \
330 "ramdisk_size=0x2000000\0" \
331 "fdt_high=0xa0000000\0" \
332 "initrd_high=0xffffffffffffffff\0" \
333 "kernel_start=0x581100000\0" \
334 "kernel_load=0xa0000000\0" \
335 "kernel_size=0x1000000\0"
337 #ifdef CONFIG_FSL_MC_ENET
338 #define CONFIG_FSL_MEMAC
339 #define CONFIG_PHYLIB
340 #define CONFIG_PHYLIB_10G
341 #define CONFIG_CMD_MII
342 #define CONFIG_PHY_VITESSE
343 #define CONFIG_PHY_REALTEK
344 #define CONFIG_PHY_TERANETICS
345 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
346 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
347 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
348 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
350 #define CONFIG_MII /* MII PHY management */
351 #define CONFIG_ETHPRIME "DPNI1"
352 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
356 #endif /* __LS2_QDS_H */